Resolved Signals
What are resolved signals and how do they work.
Resolution??? Isn’t that for solving conflicts???
1/8/2007 - L17 Resolved Siganls
Copyright 2006 - Joanne DeGroat, ECE, OSU
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Overview – Resolved Signals
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Why resolved signals?
Steps to creating a resolved signal in VHDL
Resolution Functions
Package 1164 – Standard Logic
Example of how the update of resolved signals
works.
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Busses and Wires
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What is the difference between a bus and a wire?
Wires – have only one driving source
wires
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Busses and Wires
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Busses, on the other hand,
can be driven by one or
more sources
In both cases, wires and
busses, there can be more
than one destination for the
signal
With busses, only the
device acting as source will
actually drive a value. All
others will have their
output set at high
impedance (Z).
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ENB
ENB
ENB
Copyright 2006 - Joanne DeGroat, ECE, OSU
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How do you handle Busses in an
HDL?
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First must consider the information present on
a wire and on a bus in a digital circuit.
Information present on a wire:
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Wire is limited to 2 states using TYPE BIT
High or 1 or ‘1’
Low or 0 or ‘0’
There is a transition period between the two but
High and Low are the only 2 stable states.
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Information on a Bus
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Possible state for a BUS
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Driven high (driven to a 1)
Driven low (driven to a 0)
No driving value (Z or high impedance)
Capacitive high (H)
Capacitive low (L)
Conflict (one driver driving it to a 1, another a 0) (X)
Conflict of capacitive values (W)
And other useful values
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U – Uninitialized
– - a Don’t Care
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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In an HDL need Resolution
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With multiple drivers of a signal how do you
resolve the value seen by devices using the
bus?
RESOLUTION
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How to determine the value when two or more
drivers are driving the same signal
Must look at all drivers and determine the
appropriate value to use.
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Steps needed in VHDL
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1. Declare a type for the multi-value logic system
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2. Then declare a resolution function
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function resolved (s:mv4_logic_vector) RETURN mv4_logic;
3. And then the resolved signal
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type mv4_logic is (‘X’,’Z’,’0’,’1’):
type mv4_logic_vector is array (natural range <>) of mv4_logic;
subtype mv4r_logic is resolved mv4_logic;
type mv4r_logic_vector is array (natural range <>) of mv4r_logic;
Note that you need to use a subtype declaration to incorporate
the resolution function.
So there will be both a resolved and unresolved type for the
multi-value system
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Type and Subtype Declaration BNF
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type_declaration::= full_type_declaration |
incomplete_type_declaration
full_type_declaration::= TYPE identifier IS
type_definition
incomplete_type_definition::= TYPE identifier
type_definition::= scalar_type_definition |
composite_type_definition |
access_type_definition |
file_type_definition
Can follow the BNF for a TYPE definition but find
no resolution function here
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Type and Subtype Declaration BNF
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It is, however, in the SUBTYPE definition
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subtype_declaration::=
SUBTYPE identifier IS subtype_indication
subtype_indication::=[resolution_function_name]
type_mark [constraint]
type_mark::= type_name | subtype_name
constraint::= range_constraint | index_constraint
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VHDL specification cont.
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Had declaration for a function resolved
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function resolved(s : mv4_logic_vector) RETURN mv4_logic;
Then the body of the resolution function is given in the package body
where you will find:
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TYPE mv4_logic_table IS array (mv4_logic,mv4_logic) of mv4_logic;
CONSTANT resolution_table : mv4_logic_table :=(
-- ---------------------------------- | X Z 0 1
| |
-- --------------------------------( ‘X’, ‘X’, ‘X’, ‘X’ ), --| X |
( ‘X’, ‘Z’, ‘0’, ‘1’ ), --| Z |
( ‘X’, ‘0’, ‘0’, ‘X’ ), --| 0 |
( ‘X’, ‘1’, ‘X’, ‘1’ )); --| 1 |
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And having the resolution table can write the body of the resolution func.
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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The resolution function
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function resolved (s : mv4_logic_vector) RETURN mv4_logic IS
variable result : mv4_logic := Z; – weakest state
BEGIN
IF (s’length = 1) then return s(s’low)
ELSE
FOR i IN s’range LOOP
result := resolution_table(result,s(i));
END LOOP;
END IF;
return result;
END resolved;
Execution could be shortened by adding exit when result=‘U’
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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The big picture(or the little picture)
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st
1 Driver for a
CV
Resolved
Value
‘Z’ t
nd
2 Driver for a
CV
1st Process for
a <= equation ….
2nd Process for
a <= 2nd equation ….
‘0’ t
* * *
After posting of a
transaction(s) to the
current value of one or
more of the drivers, a
vector composed of the
current values of the
drivers is sent to the
resolution function for
determination of the
resolved value.
th
n Driver for a
CV
nth Process for
a <= nth equation ….
‘Z’ t
Copyright 2006 - Joanne DeGroat, ECE, OSU
13
Completeness of a MVL package
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Having a MVL type with resolution is only
part of creating a MVL system.
ALSO need
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Overloaded function for standard operators
Type conversion functions to convert from other
type to this type and the reverse
ieee_1164 standard MVL package is a
standard package for a multi-value logic
system and contains all of these.
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Example of overloading for our 4 state
logic system
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In the declarative part of the MVL package
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function “and” (l,r : mv4_logic) RETURN mv4_logic;
In the body of the package for this MVL
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type mv4logic_table is array (mv4_logic,mv4_logic) of mv4_logic;
CONSTANT and_table : mv4logic_table := (
-- ---------------------------------- | X Z 0
1
| |
-- --------------------------------( ‘X’, ‘X’, ‘0’, ‘X’ ), --| X |
( ‘X’, ‘X’, ‘0’, ‘X’ ), --| Z |
( ‘0’, ‘0’, ‘0’, ‘0’ ), --| 0 |
( ‘X’, ‘X’, ‘0’, ‘1’ )); --| 1 |
function “and” (l,r : mv4_logic) RETURN mv4_logic IS
BEGIN
return (and_table(l,r));
END “and”;
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Use of Resolved signals
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Must use a resolved signal
type for any signals of
mode INOUT
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PORT ( ABUS : INOUT
mv4r_logic; …
Within an
ARCHITECTURE they are
needed whenever the signal
will have more than one
driver
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ARCHITECTURE abcd OF wxyz IS
…
SIGNAL a,b,c : mv4r_logic;
…
Driver 1 of a
BEGIN
a <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns;
p1: process
begin
a <= ‘Z’;
wait …
end process;
p2: process
begin
a <= ‘0’;
wait …
end process;
END abcd;
Copyright 2006 - Joanne DeGroat, ECE, OSU
Driver 2 of a
Driver 3 of a
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Standard logic 1164
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Package is online in the
course directory
Opens with comments
on the code
What is the first part of
declaring an MVL
system in a package?
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-----------------------------------
-------------------------------------------------------------------Title
Library
: std_logic_1164 multi-value logic system
: This package shall be compiled into a library
: symbolically named IEEE.
:
Developers: IEEE model standards group (par 1164)
Purpose
: This packages defines a standard for designers
: to use in describing the interconnection data types
: used in vhdl modeling.
:
Limitation: The logic system defined in this package may
: be insufficient for modeling switched transistors,
: since such a requirement is out of the scope of this
: effort. Furthermore, mathematics, primitives,
: timing standards, etc. are considered orthogonal
: issues as it relates to this package and are therefore
: beyond the scope of this effort.
:
Note
: No declarations or definitions shall be included in,
: or excluded from this package. The "package declaration"
: defines the types, subtypes and declarations of
: std_logic_1164. The std_logic_1164 package body shall be
: considered the formal definition of the semantics of
: this package. Tool developers may choose to implement
: the package body in the most efficient manner available
: to them.
:
-------------------------------------------------------------------modification history :
-------------------------------------------------------------------version | mod. date:|
v4.200 | 01/02/92 |
--------------------------------------------------------------------
Copyright 2006 - Joanne DeGroat, ECE, OSU
18
Declaration Part of the Package
PACKAGE std_logic_1164 IS
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Declare MVL logic
system types
Declare the resolution
function
Declare the resolved
type
And declare the array
types for vectors
Declare subtype of
reduced logic systems
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-------------------------------------------------------------------- logic state system (unresolved)
------------------------------------------------------------------TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak
Unknown
'L', -- Weak
0
'H', -- Weak
1
'-'
-- Don't care
);
-------------------------------------------------------------------- unconstrained array of std_ulogic for use with the resolution function
------------------------------------------------------------------TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------- resolution function
------------------------------------------------------------------FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------- *** industry standard logic type ***
------------------------------------------------------------------SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------- unconstrained array of std_logic for use in declaring signal arrays
------------------------------------------------------------------TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------- common subtypes
------------------------------------------------------------------SUBTYPE X01
IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z
IS resolved std_ulogic RANGE 'X' TO 'Z'; -('X','0','1','Z')
SUBTYPE UX01
IS resolved std_ulogic RANGE 'U' TO '1'; -('U','X','0','1')
SUBTYPE UX01Z
IS resolved std_ulogic RANGE 'U' TO 'Z'; -('U','X','0','1','Z')
Copyright 2006 - Joanne DeGroat, ECE, OSU
19
Overload operators
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All operators are
overloaded
Can find the package in
~degroat/ee762_assign/
std_1164.vhd
-------------------------------------------------------------------- overloaded logical operators
-------------------------------------------------------------------
--
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
function
FUNCTION
"and"
"nand"
"or"
"nor"
"xor"
"xnor"
"not"
l
l
l
l
l
l
l
:
:
:
:
:
:
:
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic
r
r
r
r
r
r
:
:
:
:
:
:
std_ulogic
std_ulogic
std_ulogic
std_ulogic
std_ulogic
std_ulogic
)
)
)
)
)
)
)
RETURN
RETURN
RETURN
RETURN
RETURN
return
RETURN
UX01;
UX01;
UX01;
UX01;
UX01;
ux01;
UX01;
-------------------------------------------------------------------- vectorized overloaded logical operators
------------------------------------------------------------------FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
------------
FUNCTION "or"
FUNCTION "or"
( l, r : std_logic_vector ) RETURN std_logic_vector;
( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor"
FUNCTION "nor"
( l, r : std_logic_vector ) RETURN std_logic_vector;
( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor"
FUNCTION "xor"
( l, r : std_logic_vector ) RETURN std_logic_vector;
( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
----------------------------------------------------------------------Note : The declaration and implementation of the "xnor" function is
specifically commented until at which time the VHDL language has been
officially adopted as containing such a function. At such a point,
the following comments may be removed along with this notice without
further "official" ballotting of this std_logic_1164 package. It is
the intent of this effort to provide such a function once it becomes
available in the VHDL standard.
----------------------------------------------------------------------function "xnor" ( l, r : std_logic_vector ) return std_logic_vector;
function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;
FUNCTION "not"
FUNCTION "not"
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(
(
(
(
(
(
(
( l : std_logic_vector ) RETURN std_logic_vector;
( l : std_ulogic_vector ) RETURN std_ulogic_vector;
Copyright 2006 - Joanne DeGroat, ECE, OSU
20
Type conversion functions and edge
detection
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To convert from built
in logic types of BIT
and BIT_VECTOR
And there are similar
conversion functions
for the reduced logic
systems
Also have functions for
rising and falling edge
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-------------------------------------------------------------------- conversion functions
------------------------------------------------------------------FUNCTION To_bit
( s : std_ulogic;
xmap : BIT := '0') RETURN
BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN
BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN
BIT_VECTOR;
FUNCTION To_StdULogic
FUNCTION To_StdLogicVector
std_logic_vector;
FUNCTION To_StdLogicVector
std_logic_vector;
FUNCTION To_StdULogicVector
std_ulogic_vector;
FUNCTION To_StdULogicVector
std_ulogic_vector;
( b : BIT
( b : BIT_VECTOR
) RETURN std_ulogic;
) RETURN
( s : std_ulogic_vector ) RETURN
( b : BIT_VECTOR
) RETURN
( s : std_logic_vector
) RETURN
-------------------------------------------------------------------- edge detection
------------------------------------------------------------------FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
Copyright 2006 - Joanne DeGroat, ECE, OSU
21
Now have the package body
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Starts with a header
First code is for the
resolution function
Note initial state
Note sink state
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Sink state is state
that overrides all
others
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PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------- local types
------------------------------------------------------------------TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------- resolution function
------------------------------------------------------------------CONSTANT resolution_table : stdlogic_table := (
----------------------------------------------------------| U
X
0
1
Z
W
L
H
|
|
---------------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF
(s'LENGTH = 1) THEN
RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
Copyright 2006 - Joanne DeGroat, ECE, OSU
22
The various functions
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The AND table
The OR table
-------------------------------------------------------------------- tables for logical operations
-------------------------------------------------------------------- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-----------------------------------------------------| U
X
0
1
Z
W
L
H
----------------------------------------------------( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )
-);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-----------------------------------------------------| U
X
0
1
Z
W
L
H
----------------------------------------------------( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' )
-);
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For operation on single logic values
and vectors
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Single values and
vectors
-------------------------------------------------------------------- overloaded logical operators ( with optimizing hints )
------------------------------------------------------------------FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or"
( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
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-------------------------------------------------------------------- and
------------------------------------------------------------------FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same
length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
--------------------------------------------------------------------FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same
length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
Copyright 2006 - Joanne DeGroat, ECE, OSU
24
Example of transactions on resolved
values
ENTITY ex1 IS END ex1; -- the entity

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The model
Note that there is a
resolved signal res that is
driver both by a concurrent
signal assignment
statement and in a process.
Each is a driver.
Even though the process
has two statements that
generate transactions for
res, it is one driver of res.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ARCHTIECTURE one OF ex1 IS
SIGNAL res : std_logic; -- res is a resolved signal
BEGIN
-- concurrent signal assignment statement for signal res
-- this concurrent signal assignment statement is driver 1
res <= ‘0’ after 1 ns, ‘1’ after 10 ns, ‘0’ after 20 ns;
-- this process assigns values to res and is driver 2
PROCESS
BEGIN
WAIT FOR 5 ns;
res <= ‘L’ after 1 ns;
WAIT FOR 20 ns;
res <= ‘1’ after 1 ns;
END PROCESS;
END one;
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Copyright 2006 - Joanne DeGroat, ECE, OSU
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Time 0- and time 0
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At startup simulate
each process till it
suspends
Each driver is set to
the initial value of
‘U’
Concurrent stmt is
driver 1 of res and
generates the
transactions shown
The process
immediately
suspends until 5 ns
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res ‘U’
0
Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
CV – ‘U’
(‘0’,1ns)
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
Copyright 2006 - Joanne DeGroat, ECE, OSU
26
Advance time till time when something
occurs = 1 ns


At 1 ns driver 1 (the
concurrent stmt)
goes to a value of
‘0’
Resolved value is
still a ‘U’
res ‘U’
Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
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1
0
‘0’
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
Copyright 2006 - Joanne DeGroat, ECE, OSU
27
Avdance time to 5 ns when the process
resumes


Process generates
transaction of an
‘L’ for res at 6 ns
Process then
suspends until 25
ns
res ‘U’
Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
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1
0
5
‘0’
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
CV – ‘U’
(‘L’,6ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
28
Advance time to 6 ns


Transaction on
driver 2 becomes
the current value
on driver 2
Re-evaluate
resolution
fucntion
‘U’
Dr2
‘U’
Dr1
Dr2
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5
1
0
Dr1
‘0’
‘U’
res ‘U’
6
‘0’
L
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
CV – ‘U’ CV – ‘L’
(‘L’,6ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
29
Advance time to next time



Process is
suspended until 25
ns
Transaction on
Driver 1 at 10 ns
Advance time to
10 ns and post
transaction and reevaluate resolution
function
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Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
5
1
0
‘1’
‘0’
‘U’
res ‘U’
10
6
‘0’
‘1’
L
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
CV – ‘1’
(‘0’,20ns)
CV – ‘U’ CV – ‘L’
(‘L’,6ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
30
Advance time to next time at which
something occurs


At 20 ns last
transaction for
Driver 1 is posted
Process is
suspended until
25 ns
Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
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5
1
0
‘1’
‘0’
‘U’
res ‘U’
20
10
6
‘0’
‘0’
‘1’
‘0’
CV – ‘1’
(‘0’,20ns)
CV – ‘0’
L
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
CV – ‘U’ CV – ‘L’
(‘L’,6ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
31
Adance time again, to 25 ns



At 25 ns process resumes
Generates transaction for res of (‘1’,26ns)
Process then suspens until 30 ns
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Copyright 2006 - Joanne DeGroat, ECE, OSU
32
Advance to 26 ns



Post a value of
‘1’ to res
Now resolving a
‘0’ with a ‘1’
Simulation never
goes quiescent as
the process will
always be
waiting
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Dr1
‘U’
Dr2
‘U’
Dr1
Dr2
5
1
0
‘1’
‘0’
‘U’
res ‘U’
‘0’
‘1’
‘0’
‘1’
L
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘U’
CV – ‘1’
(‘0’,20ns)
CV – ‘U’ CV – ‘L’
(‘L’,6ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
‘X’
25 26
20
10
6
‘0’
CV – ‘0’
CV – ‘L’ CV – ‘1’
(‘1’,26ns)
33
A 2nd example of transactions on
resolved values



The model is similar to the
first
Again there is a resolved
signal res that is driver
both by a concurrent signal
assignment statement and
in a process. Each is a
driver. However, this time
res is initialized to ‘1’
Again there are two drivers
of res
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ENTITY ex2 IS END ex2; -- the entity
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ARCHTIECTURE one OF ex2 IS
SIGNAL res : std_logic :=’1’; -- res is a resolved signal
BEGIN
-- this concurrent signal assignment statement is driver 1
res <= ‘0’ after 1 ns, ‘1’ after 10 ns, ‘0’ after 20 ns;
-- this process assigns values to res and is driver 2
-- and slightly different from the process in ex1
PROCESS
BEGIN
res <= ‘Z’ after 2 ns;
WAIT FOR 5 ns;
res <= ‘L’ after 25 ns;
WAIT FOR 20 ns;
res <= ‘1’ after 1 ns;
END PROCESS;
END one;
Copyright 2006 - Joanne DeGroat, ECE, OSU
34
Time 0- and time 0




At startup simulate
each process till it
suspends
Each driver is set to
the initial value of ‘1’
Concurrent stmt is
driver 1 of res and
generates the
transactions shown
Process generates the
signal transaction,
suspends until 5 ns
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res ‘1’
0
Dr1
‘1’
Dr2
‘1’
Dr1
CV – ‘1’
(‘0’,1ns)
(‘1’,10ns)
(‘0’,20ns)
Dr2
CV – ‘1’
(Z,2ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
35
Advance time till time when something
occurs = 1 ns


At 1 ns driver 1 (the
concurrent stmt)
goes to a value of
‘0’
Resolved value is
now an ‘X’
0
Dr1
‘1’
Dr2
‘1’
Dr1
Dr2
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‘X’
res ‘1’
1
‘0’
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘1’
(Z,2ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
36
Advance time till time when something
occurs = 2 ns



At 2 ns driver 2, the
res
process, is updated
with a value of ‘Z’
Dr1
for res.
Resolved value is Dr2
now an ‘0’
Dr1
Still have process
suspended until 5ns
Dr2
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‘X’
‘1’
0
‘1’
1
‘0’
2
‘0’
‘Z’
‘1’
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘Z’
Copyright 2006 - Joanne DeGroat, ECE, OSU
37
Avdance time to 5 ns when the process
resumes


Process generates
transaction of an
‘L’ for res after
25 ns or 30 ns
into simulation
Process then
suspends until 25
ns
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0
Dr1
‘1’
Dr2
‘1’
Dr1
Dr2
‘0’
‘X’
res ‘1’
5
2
1
‘0’
‘Z’
CV – ‘0’
(‘1’,10ns)
(‘0’,20ns)
CV – ‘Z’
(‘L’,30ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
38
Advance time to 10 ns



Posting
transaction on
Driver 1.
Re-evaluate
resolution
fucntion
Process 2 still
suspeneded until
25 ns.
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‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
Dr1
Dr2
1
‘0’
2
‘1’
10
5
‘0’
‘1’
‘Z’
CV – ‘1’
(‘0’,20ns)
CV – ‘Z’
(‘L’,30ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
39
Advance time to next time, 20 ns


Post transaction
on Driver 1
Process still
suspended till
25ns
‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
1
‘0’
2
‘1’
5
10
‘0’
‘1’
20
‘0’
‘Z’
CV – ‘0’
Dr1
Dr2
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CV – ‘Z’
(‘L’,30ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
40
Advance time to next time, 25 ns




Time resume
process
First generate a
transaction of
res(‘1’,26ns)
This is before the
transaction on the
project output
waveform so that
old transaction is
deleted and this new
transaction posted.
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‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
1
‘0’
2
‘1’
5
‘0’
10
‘1’
20
25
‘0’
‘Z’
CV – ‘0’
Dr1
Dr2
Copyright 2006 - Joanne DeGroat, ECE, OSU
CV – ‘Z’
(‘1’,26ns)
41
Advance time to next time, 25 ns




Process continues at
top and executes
res<=‘Z’ after 5 ns;
Generates transaction
res(‘Z’,27ns)
Now must add this
transaction to driver 2
Process then
suspends until 30 ns
‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
1
‘0’
2
‘1’
5
‘0’
‘1’
20
25
‘0’
‘Z’
CV – ‘0’
Dr1
Dr2
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10
Copyright 2006 - Joanne DeGroat, ECE, OSU
CV – ‘Z’
(‘1’,26ns)
42
Adding transaction to driver 2



Run the algorithm for posting transactions to
drivers (Lect 16).
Step 1 no at or after to delete
Step2 – append the transaction


POW – CV - res(‘1’,26ns) - res(‘Z’,27ns)
Now run part II of the algorithm
1/8/2007 - L17 Resolved
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Copyright 2006 - Joanne DeGroat, ECE, OSU
43
Part II of the Update algorithm

Step 1 - Mark new transactions


Step 2 - An old transaction is marked if it immediately
precedes a marked transactions and its value component is the
same as that of the marked transaction.




Here the values are different so it is not marked
POW – CV - res(‘1’,26ns) - Xres(‘Z’,27ns)
Step 3 – The CV is marked


POW – CV - res(‘1’,26ns) - Xres(‘Z’,27ns)
POW – xCV - res(‘1’,26ns) - Xres(‘Z’,27ns)
Step 3 – All unmarked are deleted
POW – CV - res(‘Z’,27ns)
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Copyright 2006 - Joanne DeGroat, ECE, OSU
44
Resulting in
‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
1
‘0’
2
‘1’
5
‘0’
10
‘1’
20
25
‘0’
‘Z’
CV – ‘0’
Dr1
Dr2
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CV – ‘Z’
(‘Z’,27ns)
Copyright 2006 - Joanne DeGroat, ECE, OSU
45
Advance time to 27ns



Post transaction on
Driver 2
Process suspended
until 30 ns
As values assigned
by process will
result in no change
of value will end
here.
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‘X’
res ‘1’
0
Dr1
‘1’
Dr2
‘1’
1
‘0’
2
‘1’
5
‘0’
10
‘1’
20
25
27
‘0’
‘Z’
CV – ‘0’
Dr1
CV – ‘Z’
Dr2
Copyright 2006 - Joanne DeGroat, ECE, OSU
46