An Effective DFM Strategy
Requires Accurate Process and
IP Pre-Characterization
Carlo Guardiani, Massimo Bertoletti, Nicola
Dragone, Marco Malcotti, and Patrick
McNamara
PDF Solutions Inc.
DAC 2005, Anaheim, CA
Technology Roadmap Challenges
45nm
 Lithography
 Layout pattern
65nm
90nm
 Back-end integration
Low-k
CMP
 Product ramp issues
Yield vs.
performance
dependence
 Lithography
 OPC/PSM integr. w/
photo-window
 Front-end/Transistor
 Layout dependent
performance
 Parametric variation
 Immersion litho,
 OPC/PSM integration
w/ photo window
 Front end/Transistor
 New gate/oxide
architectures
 Reliability
The Evolution of Product Yields
Yield Limiters by Technology Node
100%
Yield
90%
80%
70%
60%
Random Defect Limited Yield
50%
Design Feature Limited Yield
Total Yield
90
nm
m
0.
13
u
m
0.
18
u
m
0.
25
u
m
0.
35
u
0.
5u
m
0.
8u
m
40%
Technology

Random defects are no longer the dominant
yield loss mechanism
– Yields are limited by design features
From Reactive to Proactive DFM:
A Copernican Revolution…
Yield Revolved Around Rules



Design rules guarantee yield!…well, not
really…
…then recommended rules
…and opportunistic design data base
post-processing to enforce them
Yield Models are the driving force in the DFM universe


Accurate Yield Models Characterized
in Silicon
Fully integrated in standard design
tools and flows
Rule-based DFM?
MUX4X1AFY_Y1 - 20 tracks
MUX4X1AFY_PMSY4 - 21 tracks
25 FPB
MUX4X1AFY1_Y16 - 27 tracks
32 FPB
MUX4X1AFY_COY4 - 25 tracks
19 FPB
20 FPB
Reactive vs. Proactive DFM
Design
Verification
DRM
SPICE
IP lib.
Design
DFM & Manufacturing
Verification
Physical
Floorplan
Formal
Design
Synthesis
Place&route
Timing & SI
DFM
Optimizations
DFM
MDP
sign-off
Dummy Fill
OPC/RET
Mask Making
Manufacturing Facility
DFM & Manufacturing
Design
Verification
DRM
SPICE
IP lib.
Design
Design
Yield –aware
Synthesis
Verification
Physical
Formal
Yield
Aware
Floorplan
Yield-aware
Statistical
Place&route
Timing & SI
DFM MDP
sign-off
DFM
Tuning
Dummy Fill
OPC/RET
Mask Making
Proactive DFM

Designer access to process data is limited
–
–
–
–

DFM today is Reactive
Increased design cycle time
Risky design feature changes
Misaligned mask GDSII and design database
DFM needs to be Proactive
–
–
–
–
Up-front accurate process characterization
Occurring early in the design flow
Model based IP characterization
Manufacturable-by-construction designs
DFM characterization Of IP libraries
Process Margin
1.2
RANDOM
0.2
0.6
0.15
0.4
0.1
0.2
0.05


0.2
0.18
0.16
0.14
0.1
0.12
Litho Process Window
Yield
Extractions
Process
Margins and
Litho
calibration
data
Library
GDS
Context
Generation
ACC

0.08
0.02
Spacing
Design
Attributes
Design SYSTEMATIC
0.06
0
0.04
0
p(spacing)
Yield
0.25
0.8
0
Process
FR
(D0,l)
0.3
1
Library
GDS
Golden
OPC/RET
Lithography
Simulator
.pdfm
Characterize IP library for yield (.pdfm)
– Extract design attributes of yield models
– Include random, design systematic and
litho effects
New yield library view (.pdfm)
Enable hierarchical large capacity DFM chip analysis
Libra
ry
YIMP
ACC
.pdfm
Random Yield Loss: Physical
Mechanisms
Material
opens
Material
shorts
Type
Random
Yield Loss Mechanisms
Active, poly and metal shorts and opens due to
particle defects
Contact and via opens due to formation
defectivity
Random Yield Loss: Test Structures

Extract Metal layer open and
short defectivity

Extract Metal layer open and
short Defect Size Distribution
(DSD)
Systematic Yield Loss: Physical
Mechanisms
Via Failure Rate (fpb)
Failure Rate
160
140
120
100
80
60
40
20
0
0.4
1.8
4.2
9
Pitch (um)
Type
Systematic
Yield Loss Mechanisms
Impact of micro/macro loading design rule marginalities
Leakage from STI related stress
Contact/via opens due to local neighborhood effects
(e.g. pitch/hole size)
Misalignment, line-ends/borders
Systematic Yield Loss: Test
Structures
Without Neighborhood
With Neighborhood
To Pad A
To Pad B To Pad C
M1
STI
N+
N+
PWL
P+
Printability Yield Loss: Physical
Mechanisms
Type
Systematic
Yield Loss Mechanisms
Poor contact coverage due to misalignment and
defocus/pull back
Poly/Metal shorts
Material opens
Layout
Metric
Printability Yield Loss: Modeling
Misalignment
Misalignment
0.7
0.6
0.5
Process Margin
0.4
0.3
1.2
0.2
0.3
0.1
0.25
0
3.
s
0.2
0.6
0.15
0.4
0.1
0.2
0.05
Yield Loss
Spacing
coverage
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0
0.02
0
0
s
s
s
s
s
s
s
s
s
s
s
s
Yield
5
2.
0
2.
5
1.
0
1.
5
0.
0
0.
.5
-0
.0
-1
.5
-1
.0
-2
.5
.0
-2
-3
0.8
p(spacing)
1
0
The .pdfm View

Library characterized to
generate manufacturability
view (.pdfm)
– Random and design
systematic yield
– Litho process window

Using calibrated yield
models
Cell Characteristic
Library
View
Lay out
GDS
Schematic
P&R Footprint
SPICE
Netlist
LEF
Performance
.lib
Logic Function
Verilog
Power
Noise

Multi-layer litho process
window incorporated
…
…
Manufacturability
.pDFM
Application: IP library DFM Quality Analysis
Yield sensitivity
analysis
Cell FR Improvement (ppb)
NAND2 CELL
COAO3BTC2NOR2XC_R2
10
8
orig
6
Y1
4
Y2
2
Y3
0
Y4
-2
Y5
-4
Y6
-6
Poly Open
Poly Short
M1 Open
Process Corner


M1 Short
Dominant Process Effect
COAO3BTC2SDFFQXC_R2

Cell FR Improvement (ppb)
AOI CELL
12
10
orig
8
Y1
Y2
6
Y3
4
Y4
2
Y5
0
Y6
-2
Poly Open
Poly Short
M1 Open
ProcessCorner
Corner
Process
M1 Short

Optimal design depends on
process corner
– Ex NAND2: Y5, Y6, Y1,
Y4
Best becomes worst at
different process corner
– Ex NAND2:
Y1_m1opens vs.
Y1_m1shorts
DFM Sensitivity depends
on layout attributes
– M1 more sensitive than
Poly
Identify redundant layout
implementations
– Ex AOI: Y4, Y5
Yield aware synthesys and place&route
VERIFICATION
RTL Design
Hierarchical
Floorplan
Physical
Synthesis

Yield View (.pdfm)
Yield
Gap
Yield
Estimator
Estimation
YieldModels
Models
Yield
Yield
Optimizer
Optimization
Extended
DFM IP
Chip Assembly
Sign-off

DFM SW plug-ins
LIBRARIES
Standard Libraries
Proactive DFM
Maximize manufacturability by construction
Conclusions

Impact of design systematic and lithography yield
loss mechanisms crossed over random phenomena

Rule-based, reactive DFM is impractical

Model-based, proactive DFM is the answer
– Early in the design flow
– Find the best trade-off based on actual process
capabilities
– Before verification