Pixels with Internal Storage:
ISIS by LCFI
Andrei Nomerotski,
University of Oxford
Ringberg Workshop, 8 April 2008
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Andrei Nomerotski
Outline
 Principle of operation
 ISIS1
 ISIS2 design and status
 ISIS with 3D vertical integration
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Andrei Nomerotski
Readout for ILC
LC Beam Time Structure:
0.2 s
337 ns
2820x
0.95 ms = one train
 Massive e+e- background from beamstrahlung : pairs
radiated in intense EM fields of bunches
 Need to read out pixels in vertex detector once occupancy
= 1%
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20 times per train
 Main idea: Each pixel has a 20-cell storage
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Charge is stored INSIDE the pixel during collisions
and read out during quiet time
Andrei Nomerotski
ISIS
– In-Situ Storage Image Sensor
Ch.Damerell
 Each pixel has internal memory implemented as CCD register
 Charge collected under a photogate
 Charge is transferred to 20-pixel storage CCD in situ
 Conversion to voltage and readout in the 200 ms-long quiet
period after collisions
 Visible light imagers based on the ISIS principle are available offthe-shelf (ex. DALSA, 100 MHz camera with 16 storage cells)
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Andrei Nomerotski
 Advantages
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Store raw charge – robust to EMI issues
Slow readout after collisions
Small number of transfers – radiation hard
 Difficulty
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Non-standard process – need features of both CCD and CMOS processes
ISIS by LCFI
 LCFI successfully demonstrated proof of principle in 2007 in
ISIS1 and will submit next generation ISIS2 in May 2008
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Andrei Nomerotski
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The ISIS1
16x16 pixels, each 40x160 mm2
Five storage cells for pixel
Direct access to pixels by Row Select, no edge logic
Two variants : with and without p-well
Produced by e2V in UK

e2V had to rerun the p-well variant
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Andrei Nomerotski
ISIS Proof of Principle
K.Stefanov, RAL
 Tests with 55Fe X-ray source
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Demonstrated correct charge storage in 5 time slices and
consequent readout
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Andrei Nomerotski
ISIS1 with p-well
 High p-well doping protect
storage register
 Look at ratio R of charge
collected at photogate to
charge collected at storage
pixel
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From 55Fe (1640 e-)
 If increase clock voltage,
get punchthrough under inpixel CCD, R drops
 Lower p-well doping,
charge reflection decreases
 No p-well, R ~ 7

dependent on gate geometry
and voltages
K.Stefanov
G.Zhang, RAL
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Andrei Nomerotski
ISIS1 Testbeam
 Constructed telescope with
five ISIS1 chips
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No p-well
 Active area 0.56 x 2.22 mm2

Accurate alignment required
 Tests performed at DESY 16 GeV electron beam in Nov
2007
 Readout speed 2.5 MHz
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ILC needs 1 MHz
J.Veltius
J.Goldstein
S.Mandry, Bristol
Andrei Nomerotski
Test Beam First Results
 S/N = 37
 Position resolution in xdirection 10.8 mm
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Pitch 60 mm  some charge
sharing
Sqrt(60 mm) = 17.3 mm
Included large multiple
scattering
 Little charge sharing in ydirection (140 mm across
pixel)
 Next testbeam in August at
CERN
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Large beam energy and
EUDET telescope
 Will test ISIS1 with p-well
Correlation between measured and
predicted position
J.Veltius, Bristol
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Andrei Nomerotski
Next generation ISIS: ISIS2
 Jazz Semiconductor will manufacture ISIS2
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Process: 0.18 mm with dual gate oxide  possible voltages 1.8V and 5 V
p++ wafers with 25 mm epi layer r > 100 Ohm cm
Area 1 cm2 (four 5x5 mm2 tiles)
 Will develop buried channel and deep p+ implant
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Buried channel is necessary for CCD
Non-overlapping gates
Deep p+ is beneficial to decouple buried channel from p-well, no need for
punchthrough, was absent in ISIS1
 Cross section under Photogate:
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Andrei Nomerotski
ISIS2 Design
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Pixels 80 x 10 mm2
Buried channel 5 mm wide
3 metal layers
CCD gates: doped polysilicon
Logic, source follows use 5V
custom logic gates
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Andrei Nomerotski
ISIS2 Design
 One chip will have several variants
of ISIS2
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Each has independent control
 Row select and decoder edge logic
 Will have several test structures
 Submission in May 2008
K.Stefanov
P.Murray, RAL
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Andrei Nomerotski
ISIS2 Variations
 Reset transistor
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Surface
Buried channel
 Deep p+
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With deep p+
Without deep p+
With deep p+ but no
charge collection
hole
Change in dopant
concentrations of
~20%
 CCD gate width
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Andrei Nomerotski
Charge Collection
 Performance extensively simulated
 Charge collection:
K.Stefanov
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Andrei Nomerotski
Charge transfer
 Simulated charge transfer to photogate and to storage
cells – all function with high efficiency
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K.Stefanov
Andrei Nomerotski
3D ISIS Concept
 Discussed implementation of
ISIS with MIT Lincoln Labs –
one of the options was a 3D
ISIS
 3D ISIS has two Tiers
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1st Tier : Storage (CCD) part
2nd Tier : Readout (CMOS) part
 Zigzag CCD register controlled
by linear gates
 CCD clock distribution in CCD
tier
A.Nomerotski
K.Stefanov
F1
F2
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Andrei Nomerotski
Summary
 ISIS concept: pixels with storage in a mini CCD
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Easier for light, difficult for particles
 LCFI demonstrated proof of principle of ISIS in ISIS1
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Collection of charge through photogate
Shielding of CCD register by p-well
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Tested in testbeam
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 Nest generation sensor ISIS2 should be available by
the end of the year
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Andrei Nomerotski
Backups
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Andrei Nomerotski
ISIS1 Charge Collection
 Charge is collected through a
punchthrough in p-well
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