TMMS04_EM_1
An MOSFET transistor IRFB7540 from International Rectifier is used in a high-side configuration
for controlling a inductive load. The current is controlled by a PWM-signal to the gate-driver
connected to the gate (G) of the transistor. The supply-rail hold 48V. The internal resistance of the
load is 8.4 ohm. What is the expected power dissipation in the transistor and PWM duty cycle
when the load drains 30W from the supply rail?
TMMS04_EM_2
An integrated DMOS full-bridge motor driver (Allegro Micro Systems A3949) is used for driving a
FAULHABER DC-micromotor series 3272CR. The applications is similar to an elevator. The
arrangement lifts a load of 2.4kg using a wire-on-drum configuration. The diameter of the winch
drum is 12cm. There is a FAULHABER planetary gear head glued to the motor. It is of series 38A
with a gear ratio of 20, double stages. What lifting speed can be expected at stationary conditions
using a large 24V power supply? The gearbox does not operate at ideal conditions but att an 85%
efficiency. However, the motor may be assumed to operate at maximum efficiency.
A3949
DMOS Full-Bridge Motor Driver
Features and Benefits
Description
Single supply operation
Very small outline package
Low RDS(ON) outputs
Sleep function
Internal UVLO
Crossover current protection
Thermal shutdown protection
Designed for PWM (pulse width modulated) control of DC
motors, the A3949 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM control signals. Internal synchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
Packages:
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VBB and VCP , and
crossover current protection.
The A3949 is supplied in a power package, a 16-pin plastic SOIC
with a copper batwing tab (part number suffix LB). The packages
are lead (Pb) free, with 100% matte tin leadframes.
Package LB, 16-pin SOIC
with internally fused pins
Not to scale
Functional Block Diagram
.22 µF
25 V
0.1 µF
VREG
Low Side
Gate Supply
CP1
OSC
Charge
Pump
CP2
VCP
0.1 µF
VBB
Load
Supply
MODE
0.1 µF
PHASE
OUTA
Control
Logic
OUTB
ENABLE
SENSE
SLEEP
DMOS Full Bridge
GND
GND
29319.47i
100 µF
DMOS Full-Bridge Motor Driver
A3949
Selection Guide
Part Number
A3949SLBTR-T
Package
Packing
16-pin, SOIC
1000 per reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Input Voltage
VIN
Sense Voltage
Notes
Peak < 2 s
IOUT
V
38
V
V
0.5
V
±2.8
A
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, DO NOT exceed the specified
IOUT or TJ.
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
Units
36
–0.3 to 7
VSENSE
Output Current, Repetitive
Rating
Package Thermal Characteristics*
Characteristic
Symbol
R
Note
Package Thermal Resistance
Measured on 2-layer PCB with 2 in. 2-oz. copper each side
JA
*Additional information is available on the Allegro website.
2
Rating
Units
52
°C/W
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
DMOS Full-Bridge Motor Driver
A3949
ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 8 V to 36 V (unless otherwise noted)
Characteristics
Min.
Typ.
Max.
Source driver, IOUT = –2.8 A, TJ= 25°C
–
.4
.48
Source driver, IOUT = –2.8 A, TJ= 125°C
–
.68
–
Sink driver, IOUT = 2.8 A, TJ= 25°C
–
.3
.43
Sink driver, IOUT = –2.8 A, TJ= 125°C
–
.576
–
Source diode, IF = –2.8 A
–
1.1
1.3
V
Sink diode, IF = 2.8 A
–
1
1.3
V
fPWM < 50 kHz
–
6
8.5
mA
Charge pump turned on; outputs disabled
–
3
4.5
mA
Sleep mode
–
–
10
A
VIN(1)
2.0
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Voltage
SLEEP
VIN(1)
2.7
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Current
PHASE, MODE pins
IIN(1)
VIN = 2.0 V
–
< 1.0
20
A
IIN(0)
VIN = 0.8 V
–
< –2.0
–20
A
Logic Input Current
ENABLE pin
IIN(1)
VIN = 2.0 V
–
40
100
A
IIN(0)
VIN = 0.8 V
–
16
40
A
Logic Input Current
SLEEP pin
IIN(1)
VIN = 2.7 V
–
27
50
A
IIN(0)
VIN = 0.8 V
–
<1
10
A
From PWM change to source or sink turn on
–
600
–
ns
From PWM change to source or sink turn off
–
100
–
ns
–
500
–
ns
–
6
–
V
–
250
–
mV
–
170
–
°C
–
15
–
°C
Output-On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Input Voltage
PHASE, ENABLE, MODE
Propagation Delay Times
Crossover Delay
Symbol
RDSON
VF
IBB
tpd
Test Conditions
tCOD
Units
Protection Circuitry
UVLO Enable Threshold
VBB rising
UVLO Hysteresis
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
TJ
TJ
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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3
DMOS Full-Bridge Motor Driver
A3949
PWM Control Timing Diagram
SLEEP
ENABLE
PHASE
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
8
9
VBB
VBB
6
7
OUTB
OUTA
1
OUTA
OUTB
5
9
3
2
8
4
A
Charge pump and VREG power-up delay (approximately 200 us)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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4
DMOS Full-Bridge Motor Driver
A3949
Functional Description
VREG. This supply voltage is used to operate the sinkside DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 F
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driving the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this configuration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by VBEMF / RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
Control Logic Table
PHASE ENABLE MODE
SLEEP
OUTA
OUTB
Function
1
1
X
1
H
L
Forward
0
1
X
1
L
H
Reverse
X
0
1
1
L
L
Brake (slow decay)
1
0
0
1
L
H
Fast decay SR*
0
0
0
1
H
L
Fast decay SR*
X
X
X
0
Hi-Z
Hi-Z
Sleep mode
* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs
go to the high impedance state as the current approaches zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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5
DMOS Full-Bridge Motor Driver
A3949
LB Package
N/C
1
16 N/C
MODE
2
15 VREG
PHASE
3
14 VCP
GND
4
13 GND
SLEEP
5
12 CP2
ENABLE
6
11
OUTA
7
10 OUTB
SENSE
8
9
Name
N/C
Description
CP1
VBB
Number
Not used
1
MODE
Logic input
2
PHASE
Logic input for direction control
3
Ground
4*
SLEEP
Logic input
5
ENABLE
Logic input
6
Output A for full bridge
7
Power return
8
Load supply voltage
9
OUTB
Output B for full bridge
10
CP1
Charge pump capacitor
11
CP2
Charge pump capacitor
12
GND
Ground
13*
VCP
Reservoir capacitor
14
Low side gate supply decoupler
15
Not used
16
GND
OUTA
SENSE
VBB
VREG
N/C
*These pins are internally connected.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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6
DMOS Full-Bridge Motor Driver
A3949
LB 16-Pin SOICW
10.30
4º
1.27
0.65
16
0.27
7.50
10.30
9.50
A
0.84
2.25
1
2
B
0.25
16X
SEATING
PLANE
0.10 C
0.41
1.27
C
All dimensions nominal, not for tooling use
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Pins 4 and 13 fused internally
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20
PCB Layout Reference View
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2003-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
StrongIRFET™
IRFB7540PbF
IRFS7540PbF
IRFSL7540PbF
HEXFET® Power MOSFET
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
VDSS
D
60V
RDS(on) typ.
4.2m
max
5.1m
G
S
ID
110A
D
D
Benefits
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free, RoHS Compliant
S
D
G
S
G
TO-220AB
IRFB7540PbF
IRFB7540PbF
IRFSL7540PbF
IRFS7540PbF
TO-220
TO-262
D2-Pak
S
Source
Orderable Part Number
IRFB7540PbF
IRFSL7540PbF
IRFS7540PbF
IRFS7540TRLPbF
120
14
ID = 65A
100
12
10
T J = 125°C
8
6
80
60
40
20
4
T J = 25°C
0
2
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
D
Drain
Standard Pack
Form
Quantity
Tube
50
Tube
50
Tube
50
Tape and Reel Left
800
ID, Drain Current (A)
RDS(on), Drain-to -Source On Resistance (m
)
Package Type
S
D
TO-262
IRFSL7540PbF
D2Pak
IRFS7540PbF
G
Gate
Base part number
G
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© 2014 International Rectifier
25
50
75
100
125
150
175
TC , Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
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January 10, 2014
IRFB/S/SL7540PbF
Absolute Maximum Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
Parameter
Max.
Continuous Drain Current, VGS @ 10V
110
Continuous Drain Current, VGS @ 10V
80
Pulsed Drain Current
430
Maximum Power Dissipation
160
Linear Derating Factor
1.1
VGS
Gate-to-Source Voltage
± 20
TJ
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Mounting Torque, 6-32 or M3 Screw
10 lbf·in (1.1 N·m)
Avalanche Characteristics
180
EAS (Thermally limited)
Single Pulse Avalanche Energy
65
EAS (tested)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
See Fig 15, 16, 23a, 23b
Repetitive Avalanche Energy
EAR
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Junction-to-Case
R JC
–––
0.95
Case-to-Sink, Flat Greased Surface (TO-220)
R CS
0.50
–––
Junction-to-Ambient (TO-220)
R JA
–––
62
Junction-to-Ambient (PCB Mount) (D2Pak)
R JA
–––
40
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
V(BR)DSS/ TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
Min.
60
–––
–––
–––
2.1
–––
–––
–––
–––
–––
Units
A
W
W/°C
V
°C
mJ
A
mJ
Units
°C/W
Typ. Max. Units
Conditions
––– –––
V VGS = 0V, ID = 250µA
48
––– mV/°C Reference to 25°C, ID = 1mA
4.2
5.1
VGS = 10V, ID = 65A
m
5.4
–––
VGS = 6.0V, ID = 33A
–––
3.7
V VDS = VGS, ID = 100µA
–––
1.0
VDS = 60V, VGS = 0V
µA
––– 150
VDS = 60V,VGS = 0V,TJ =125°C
––– 100
VGS = 20V
nA
––– -100
VGS = -20V
2.2
–––
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 86µH, RG = 50 , IAS = 65A, VGS =10V.
ISD 65A, di/dt 1130A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as C oss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
This value determined from sample failure population, starting TJ =25°C, L= 86µH, RG = 50 , IAS = 65A, VGS =10V.
2
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January 10, 2014
IRFB/S/SL7540PbF
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg – Qgd)
Turn-On Delay Time
Rise Time
Min.
110
–––
–––
–––
–––
–––
–––
Typ.
–––
88
22
28
60
12
76
td(off)
Turn-Off Delay Time
–––
58
tf
Ciss
Coss
Crss
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance
(Energy Related)
Output Capacitance (Time Related)
–––
–––
–––
–––
56
4555
415
270
–––
430
–––
VGS = 0V, VDS = 0V to 48V
–––
550
–––
VGS = 0V, VDS = 0V to 48V
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min.
Typ.
Max. Units
–––
–––
110
–––
–––
430
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
VSD
Diode Forward Voltage
–––
–––
1.2
dv/dt
Peak Diode Recovery dv/dt
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
–––
–––
–––
–––
–––
–––
11
33
37
36
47
1.9
–––
–––
–––
–––
–––
–––
Coss eff.(ER)
Coss eff.(TR)
Max. Units
Conditions
–––
S VDS = 10V, ID = 65A
130
ID = 65A
–––
VDS = 30V
nC
–––
VGS = 10V
–––
–––
VDD = 30V
–––
ID = 65A
ns
–––
RG= 2.7
VGS = 10V
–––
–––
–––
–––
pF
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig.7
Diode Characteristics
Symbol
IS
ISM
3
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© 2014 International Rectifier
A
V
D
G
S
TJ = 25°C,IS = 65A,VGS = 0V
V/ns TJ = 175°C,IS = 65A,VDS = 60V
TJ = 25°C
VDD = 51V
ns
TJ = 125°C
IF = 65A,
TJ = 25°C di/dt = 100A/µs
nC
TJ = 125°C
A TJ = 25°C
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IRFB/S/SL7540PbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
10
4.5V
1
60µs PULSE WIDTH
BOTTOM
4.5V
10
60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
0.1
1
0.1
1
10
100
1000
0.1
V DS, Drain-to-Source Voltage (V)
10
100
1000
Fig 4. Typical Output Characteristics
2.4
100
TJ = 175°C
10
TJ = 25°C
1
V DS = 25V
60µs PULSE WIDTH
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
Fig 3. Typical Output Characteristics
ID = 65A
V GS = 10V
2.0
1.6
1.2
0.8
0.4
0.1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20 0 20 40 60 80 100120140160180
8.0
TJ , Junction Temperature (°C)
V GS, Gate-to-Source Voltage (V)
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + Cgd, C ds SHORTED
ID = 65A
V GS, Gate-to-Source Voltage (V)
C rss = C gd
C oss = Cds + Cgd
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10000
Ciss
Coss
Crss
1000
12.0
V DS= 48V
V DS= 30V
10.0
V DS= 12V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
0
20
40
60
80
100
V DS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
Fig 8. Typical Gate Charge vs.
Gate-to-Source Voltage
4
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120
January 10, 2014
IRFB/S/SL7540PbF
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
TJ = 25°C
10
100
OPERATION
IN THIS
AREA
LIMITED BY
R DS(on)
10
1
DC
0.1
0.2
0.6
1.0
1.4
1.8
0.1
V SD, Source-to-Drain Voltage (V)
1
10
VDS, Drain-to-Source Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
0.8
78
Id = 1.0mA
0.7
76
0.6
74
Energy (µJ)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V GS = 0V
1.0
100µsec
1msec
72
70
0.5
0.4
0.3
0.2
68
0.1
0.0
66
0
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( m )
10
Fig 12. Typical Coss Stored Energy
14
12
Vgs = 5.5V
Vgs = 6.0V
Vgs = 7.0V
Vgs = 8.0V
Vgs = 10V
10
8
6
4
2
0
40
80
120
160
200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFB/S/SL7540PbF
Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart = 25°C (Single Pulse)
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
j = 25°C and
Tstart = 150°C.
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 65A
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 14)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2 T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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IRFB/S/SL7540PbF
12
3.5
2.5
2.0
ID = 100µA
ID = 250µA
1.5
ID = 1.0mA
ID = 1.0A
8
TJ = 125°C
6
4
2
1.0
0.5
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
TJ , Temperature ( °C )
diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
200
12
IF = 43A
V R = 51V
IF = 65A
V R = 51V
10
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
150
QRR (nC)
8
IRRM (A)
10
IF = 43A
V R = 51V
TJ = 25°C
3.0
IRRM (A)
V GS(th) , Gate threshold Voltage (V)
4.0
6
100
4
50
2
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/µs)
diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt
Fig 20. Typical Stored Charge vs. dif/dt
200
IF = 65A
V R = 51V
TJ = 25°C
150
QRR (nC)
TJ = 125°C
100
50
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
7
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IRFB/S/SL7540PbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
IAS
20V
tp
+
V
- DD
A
I AS
0.01
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Qgs1 Qgs2
Fig 25a. Gate Charge Test Circuit
8
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Qgd
Qgodr
Fig 25b. Gate Charge Waveform
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IRFB/S/SL7540PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
EXAM PLE:
T H IS IS A N IR F 1 0 1 0
LO T C O D E 1789
ASSEM BLED O N W W 19, 2000
IN T H E A S S E M B L Y L IN E "C "
N o t e : "P " in a s s e m b ly lin e p o s it io n
in d ic a t e s "L e a d - F r e e "
IN T E R N A T IO N A L
R E C T IF IE R
LO G O
ASSEM BLY
LO T C O D E
PART NUM BER
D ATE C O D E
YEA R 0 = 2000
W EEK 19
L IN E C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFB/S/SL7540PbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
ASSEMBLED ON WW19, 1997
IN THE ASSEMBLYLINE "C"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASSEMBLYSITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFB/S/SL7540PbF
D2Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches))
D2Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFB/S/SL7540PbF
D2Pak (TO-263AB) Tape & Reel Information (Dimensions are shown in millimeters (inches))
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Qualification Information†
Industrial
(per JEDEC JESD47F) ††
Qualification Level
Moisture Sensitivity Level
TO-220
N/A
D2Pak
MSL1
TO-262
N/A
Yes
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
††
Applicable version of JEDEC standard at the time of product release.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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Planetary Gearheads
20 Nm
For combination with
DC-Micromotors
Brushless DC-Motors
Series 38A
38A
steel
steel
Housing material
Geartrain material
Recommended max. input speed for:
– continuous operation
Backlash, at no-load
Bearings on output shaft
Shaft load, max.:
– radial (14,5 mm from mounting face)
– axial
Shaft press fit force, max.
Shaft play
– radial (14,5 mm from mounting face)
– axial
Operating temperature range
Specifications
Number of gear stages
Continuous torque
Intermittent torque
Mass without motor, ca.
Efficiency, max.
Direction of rotation, drive to output
4 500 rpm
≤ 0,6 °
ball bearings
≤ 200 N
≤ 200 N
≤ 490 N
≤ 0,02 mm
≤ 0,3 mm
- 25 ... + 90 °C
Nm
Nm
g
%
1
6
9,6
190
96
=
4:1
5:1
Reduction ratio
(exact)
L2 [mm] = length without motor
L1 [mm] = length with motor 3242G...CR
3257G...CR
3272G...CR
3863H...CR
3890H...CR
3564K...B
4490H...B
4490H...BS
Orientation with respect to motor
terminals not defined
42,2
78,8
93,8
108,8
113,6
132,2
106,2
139,6
139,6
2
20
32
260
94
=
12:1
16:1
20:1
55,0
91,6
106,6
121,6
126,4
145,0
119,0
152,4
152,4
2
18
29
260
94
=
3
20
32
330
90
=
25:1
55,0
91,6
106,6
121,6
126,4
145,0
119,0
152,4
152,4
36:1
45:1
60:1
80:1
100:1
120:1
160:1
67,6
104,2
119,2
134,2
139,0
157,6
131,6
165,0
165,0
3
18
29
330
90
=
4
20
32
410
80
=
200:1
67,6
104,2
119,2
134,2
139,0
157,6
131,6
165,0
165,0
4
18
29
410
80
=
240:1
360:1
480:1
800:1
1 600:1
80,2
116,8
131,8
146,8
151,6
170,2
144,2
177,6
177,6
80,2
116,8
131,8
146,8
151,6
170,2
144,2
177,6
177,6
Scale reduced
For more combinations see table.
Example of combination with 3863...C.
4x M3 5 deep
ø0,3 A
ø38 -0,2
0
ø26 -0,021
0
ø10 -0,015
A
Flat key
DIN 6885
A3x3x18
DIN 332-DS
M3 9 deep
23 ±0,2
2,5 ±0,2
2 ±0,2
+0,3
L2 - 0,4
ø31
L1 ±1
26 ±0,3
38A
For notes on technical data and lifetime performance
refer to “Technical Information”.
Edition 2014
© DR. FRITZ FAULHABER GMBH & CO. KG
Specifications subject to change without notice.
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DC-Micromotors
120 mNm
Graphite Commutation
For combination with
Gearheads:
30/1, 30/1 S, 32/3, 32/3 S, 32A, 32ALN, 38/1, 38/1 S,
38/2, 38/2 S, 38A
Encoders:
HEDL 5540, HEDM 5500, HEDS 5500, HEDS 5540,
IE3-1024, IE3-1024 L
Series 3272 ... CR
Values at 22°C and nominal voltage
1 Nominal voltage
2 Terminal resistance
3 Output power
4 Efficiency, max.
5 No-load speed
6 No-load current, typ. (with shaft ø 5 mm)
7 Stall torque
8 Friction torque
9 Speed constant
10 Back-EMF constant
11 Torque constant
12 Current constant
13 Slope of n-M curve
14 Rotor inductance
15 Mechanical time constant
16 Rotor inertia
17 Angular acceleration
3272 G
UN
R
P2nom.
18 Thermal resistance
19 Thermal time constant
20 Operating temperature range:
– motor
– winding, max. permissible
21 Shaft bearings
22 Shaft load max.:
– with shaft diameter
– radial at 3 000 rpm (3 mm from bearing)
– axial at 3 000 rpm
– axial at standstill
23 Shaft play
– radial
– axial
24 Housing material
25 Mass
26 Direction of rotation
27 Speed up to
28 Number of pole pairs
29 Magnet material
Rth1 / Rth2
w1 / w2
Rated values for continuous operation
30 Rated torque
31 Rated current (thermal limit)
32 Rated speed
Note:
012 CR
12
0,2
164
85
5 400
0,191
1 192
3,9
459
2,18
20,8
0,048
4,4
45
3,1
67
178
max.
n0
I0
MH
MR
kn
kE
kM
kI
n/ M
L
J
m
max.
≤
=
nmax.
024 CR
24
0,82
167
87
5 500
0,095
1 188
3,9
230
4,35
41,6
0,024
4,5
185
3
63
189
048 CR
48
3,35
167
88
5 500
0,048
1 177
3,9
115
8,7
83,3
0,012
4,6
740
2,9
60
196
V
Ω
W
%
rpm
A
mNm
mNm
rpm/V
mV/rpm
mNm/A
A/mNm
rpm/mNm
µH
ms
gcm²
·10³rad/s²
2,3 / 7
40 / 850
K/W
s
-30 ... +125
+155
ball bearings, preloaded
°C
°C
5
50
5
50
mm
N
N
N
0,015
0
steel, black coated
312
clockwise, viewed from the front face
6 000
1
NdFeB
mm
mm
g
rpm
75
4
5 110
MN
IN
nN
119
3,5
5 150
120
1,7
5 180
mNm
A
rpm
Rated values are calculated with nominal voltage and at a 22°C ambient temperature. The Rth2 value has been reduced by 25%.
Note:
The diagram indicates the recommended
speed in relation to the available torque
at the output shaft for a given ambient
temperature of 22°C.
The diagram shows the motor in a
completely insulated as well as thermally
coupled condition (R th 2 50% reduced).
The nominal voltage (U N ) curve shows
the operating point at nominal voltage
in the insulated and thermally coupled
condition. Any points of operation above
the curve at nominal voltage will require
a higher operating voltage. Any points
below the nominal voltage curve will
require less voltage.
n [rpm]
3272G048CR
3272G048CR (Rth2 -50%)
Intermittent operation
Operating point
at nominal value
Watt
8 000
25
45
65
85
7 000
6 000
UN
5 000
4 000
3 000
2 000
1 000
M [mNm]
0
0
30
60
90
120
150
Recommended operation areas (example: nominal voltage 48V)
For notes on technical data and lifetime performance
refer to “Technical Information”.
Edition 2014
Page 1/2
© DR. FRITZ FAULHABER GMBH & CO. KG
Specifications subject to change without notice.
www.faulhaber.com
Dimensional drawing
Orientation with respect to motor
terminals not defined
0
-0,006
ø5 -0,010 ø13 -0,05
M3 3 deep
ø8
6x
ø0,3 A
0
ø30 -0,05
0
ø32 -0,1
0
ø16 -0,015
-0,006
0,5
ø5 -0,010
A
ø8
ø0,05 A
0,02
21
1,5
6x 60°
3,4
ø22
+0,2
- 0,3
1,5
3 ±0,15
5
9 ±0,4
72
3272 G ... CR
For notes on technical data and lifetime performance
refer to “Technical Information”.
Edition 2014
Page 2/2
10 ±0,3
13 ±0,3
3,5
2,8
7
11,6 ±0,5
for Faston connector
2,8 x 0,5
© DR. FRITZ FAULHABER GMBH & CO. KG
Specifications subject to change without notice.
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