IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
127
Superior Hot Carrier Reliability of Single Halo (SH)
Silicon-on-Insulator (SOI) nMOSFET
in Analog Applications
Najeeb-ud-din Hakim, V. Ramgopal Rao, Senior Member, IEEE, Juzer Vasi, Senior Member, IEEE, and
Jason C. S. Woo, Senior Member, IEEE
Abstract—In this paper, for the first time, we report a study on
the hot carrier reliability performance of single halo (SH) thin film
silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal
applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output
characteristics and experimental characterization results on these
devices show better th – roll-off, low DIBL, higher breakdown
voltages, and kink-free operation. Further SH SOI MOSFETs have
been shown to exhibit reduced parasitic bipolar junction transistor
effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance,
and better dynamic intrinsic gain (
) in comparison with the
conventional homogeneously doped SOI MOSFETs. Also, the low
drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs
exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device
simulations, the lower hot carrier degradation mechanism in SH
SOI MOSFETs is analyzed and compared with the conventional
SOI MOSFETs.
Index Terms—Channel hot carrier, mixed-signal applications,
silicon-on-insulator technology, single halo, thin film devices.
I. INTRODUCTION
I
N deep-submicron technologies, the RF CMOS has become
a reality. However, the challenge is to integrate the analog
functions with digital logic on a single chip, in what is known
as mixed-mode systems. The requirement for combining analog
and digital functions on the same chip has been necessitated
by the current demands in mobile communications and other
system-on-chip requirements. For system-on-chip applications,
Manuscript received January 2, 2004; revised September 11, 2004.
N. Hakim was with the Electrical Engineering Department, Indian Institute of
Technology (IIT), Bombay, Powai, Mumbai 400076, India. He is now with the
Electronics and Communications Engineering Department, National Institute of
Technology, Srinagar 190 006, India (e-mail: hnds@rediffmail.com).
V. R. Rao was with the Electrical Engineering Department, University of
California, Los Angeles, CA 9009 USA. He is now with the Electrical Engineering Department, Indian Institute of Technology (IIT), Bombay, Powai,
Mumbai 400076, India (e-mail: rrao@ee.iitb.ac.in).
J. Vasi is with the Electrical Engineering Department, Indian Institute
of Technology (IIT), Bombay, Powai, Mumbai 400076, India (e-mail:
jvasi@ee.iitb.ac.in).
J. C. S. Woo is with the Electrical Engineering Department, University of
California, Los Angeles, CA 90095 USA (e-mail: woo@ee.ucla.edu).
Digital Object Identifier 10.1109/TDMR.2005.843832
requirements are high integration density, low power dissipation, and good isolation, which can readily be achieved with silicon-on-insulator (SOI) technology [1]. The SOI technology has
also shown great potential for mixed-mode and analog applications [2]. SOI also offers potential for high-speed applications.
One challenge in mixed-mode design is to make the analog part
of the system less vulnerable to the noisy digital logic. This adversely affects the performance of analog circuits and degrades
the various parameters like signal to noise ratio. SOI structure
introduces dramatic improvement in noise decoupling between
digital and analog circuits on the same substrate, because of
buried oxide [2]. The analog SOI MOS switch has shown distinct advantages in comparison to bulk [3]. SOI technology offers various advantages including reduced short-channel effects
(SCE), better radiation performance, and immunity to latch-up,
and is likely to become a mainstream CMOS technology [4].
Typically, CMOS device design has been optimized for digital applications even for aggressively scaled channel length devices. However, the same rules may produce a poor analog performance due to SCE. Thus, it becomes necessary to optimize
the existing CMOS logic technologies, so that they are compatible with the conventional CMOS process, and at the same
time lead to improved performance in mixed-mode systems.
MOSFET device design has been engineered by different approaches for the alleviation of these disadvantages. Different
approaches like source/drain engineering, channel engineering
and gate work function engineering have been implemented for
the alleviation of these disadvantages. Channel engineering has
been widely used to improve the short-channel performance.
Asymmetric single halo (SH) MOSFET structures have been introduced for bulk [5], [6] as well as for SOI MOSFETs [7], [8] to
adjust the threshold voltage and improve the device SCE and hot
carrier effects (HCEs). These devices also achieve higher drive
currents by exploiting the velocity overshoot phenomenon [5],
which is an advantage in mixed-mode analog/digital circuits.
The reliability performance of SOI MOSFETs is crucial for
their use in deep-submicron technology. Until recently, reliability implications of MOSFETs in analog domain have not
been reported much, because of the long-channel transistors
being used. Reliability studies have previously been performed
on channel-engineered bulk devices under digital operation [9],
[10] and it has been found that SH bulk devices outperform the
conventional (CON) homogeneously doped devices. The reliability implications of SH bulk pMOSFETs under analog operating conditions have also been reported [11]. It is therefore
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128
Fig. 1.
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
Structure of an SH SOI nMOSFET.
necessary to evaluate the analog reliability implications of CON
and SH SOI nMOSFETs, which is reported in this paper. In this
paper, we have shown that SH SOI nMOSFETs have superior
hot carrier reliability performance in comparison to CON devices. The other advantages of SH over CON SOI MOSFETs,
such as absence of kink, lower inherent parasitic bipolar junction transistor (pBJT) gain have also been reported elsewhere
in detail [12], [13]. The superior small-signal characteristics for
mixed-mode applications of deep-submicron thin film SH SOI
MOSFETs have also been reported in detail [14].
II. DEVICE FABRICATION
The schematic cross section of a typical SH SOI n-type
MOSFET is shown in Fig. 1. The devices used in this work are
fabricated on SIMOX wafers. Standard CMOS technology has
been used for the fabrication. The channel implant for the CON
SOI MOSFETs is done before the gate oxidation, whereas the
implant for the SH SOI devices is done after gate formation, at
different tilt angles of 7 , 10 , and 15 . The polysilicon gate dimensions were defined by electron-beam (E-beam) lithography.
The gate oxide thickness is 3.9 nm. The silicon film used in this
of 35, 50, and 65 nm and a buried
work had thicknesses
oxide thickness of 180 nm. The devices had a source/drain
extension in addition to deep source/drain junction. A two-step
titanium silicidation process with Ge pre-amorphization was
used to control the silicide depth and reduce the contact resistance [7]. Fig. 2 shows the simulated doping profile in the
lateral direction along the channel for a 0.1 m and 0.5 m
nMOSFET. It shows the heavy doping near the source with
the rest of the channel lightly doped. The doping profiles were
obtained from process simulator TSUPREM4 [15] by using
actual process parameters as used in their fabrication.
III. CHANNEL HOT CARRIER (CHC) IN SOI AND ANALOG
MODES OF OPERATION
The hot-carrier-induced degradation in SOI devices is more
complex than that of bulk devices due to the presence of two
interfaces. The aggressive scaling of devices further aggravates
this problem because of increase in the electric fields. The high
electric field can provide sufficient energy to the channel carriers
so as to cause impact ionization. The large number of highly energetic carriers will damage not only the front interface, but also
the back interface. In fully depleted devices the carrier transport
at one interface will be affected by the defects generated at the
other interface. The most common degradation is the threshold
Fig. 2.
Doping profiles along the channel for SH (0.1 and 0.5 m), Tilt =
15 , and CON SOI nMOSFETs, 5 nm below the interface.
voltage shift by the charges trapped at the opposite oxide interface because of interface coupling effects [16]. The poor electrical properties of the buried oxide can degrade the performance
more than the front interface. However, a thin SOI film gives rise
to reduced carrier temperature [17]. The inversion layer thickness increases with decrease in film thickness, which results in
a decrease of maximum electron temperature [18] and the SOI
device can then give better hot-carrier immunity.
In digital domain the time degradation dependence of HCEs
in MOSFETs have thoroughly been investigated. Hot-carrier
generation kinetics has been investigated in detail for bulk
and SOI MOSFETs and it was observed that transconductance
degradation follows a power-law with respect to time [19]. It
is followed for both electron
has been demonstrated that
or hole injection. With the advent of SOI technology it was
possible to inject only pure electrons or pure holes in to the
gate oxide by opposite channel charge-based injection technique [20]. An empirical extrapolation technique based on
power-time dependence law was proposed [21] for predicting
the lifetime of devices. Further, a logarithmic saturation relative
to the initial power-time dependent law has been observed
in long stress time regime for all stress conditions, and the
relationship was found to be independent of channel length.
The worst hot-carrier degradation in SOI MOSFETs occurs
at lower gate voltages (few hundred millivolts above threshold),
and degradation is almost independent of the value of drain
voltage [22], [23]. Hence, the hot-carrier reliability performance
of SOI MOSFETs is crucial when operated in analog mode, because MOSFET devices in analog circuits are operated at lower
gate overdrive voltages.
To evaluate the hot-carrier reliability performance of MOS
devices in analog operation, a different approach has to be followed compared to the evaluation in digital domain, because the
operating points of MOS transistors in digital and analog CMOS
circuits differ significantly. The different degradation mechanisms which affect the device under analog operating conditions are channel hot carrier (CHC) stress, bias temperature (BT)
stress, and oxide stress [24]. Among these, CHC stress and BT
stress need specific analog approaches. This is necessary to reveal the relevant information for analog operation.
In digital operations, circuit delay is the dominant circuit parameter; therefore, drain current drive capability is the most
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HAKIM et al.: SUPERIOR HOT CARRIER RELIABILITY OF SINGLE HALO SOI NMOSFET IN ANALOG APPLICATIONS
important device parameter to be considered as a measure of
degradation. No doubt this is an important parameter in the
analog case as well, but we have to also consider device parameters like threshold voltage, and small-signal parameters like
transconductance and drain conductance, which have direct implications on the performance of an analog circuit. In an analog
circuit good matching is an essential demand, as paired or exactly weighed devices are used, whose properties will determine
the accuracy of differential stages and current mirrors. Degradation in the threshold voltage and drain current will increase the
mismatch between analog-paired devices. This will adversely
affect the offsets, accuracy, and resolution of the circuit. The
other CHC-induced degradations occur in gain, frequency response, harmonic distortion, and linearity, due to the degradaand differential drain
tion of small-signal transconductance
conductance
of the device.
IV. EXPERIMENTAL RESULTS
To study the CHC stress under analog operations, the device
parameters of importance are transconductance, output conductance, drain current under linear and saturation bias conditions,
and intrinsic gain. Due to the absence of body contact in SOI
and
)
MOSFETs, it is not easy to find the bias points (
at which the maximum CHC damage will take place, i.e., where
normally the maximum substrate current occurs. The devices
under consideration were stressed at two different bias points.
For analog applications, the devices are operated in saturation
. Hence,
with gate voltage at few hundred millivolts above
a stressing voltage of
V and
V
m. Another bias
was selected for a device having
point was also chosen, assuming that the worst case for CHC
[25]. Here the
degradation is approximately at
devices were stressed up to 10 000 s to find the time dependence of the degraded parameters. The crucial analog parameters, transconductance, and output resistance were measured
under the small-signal analog operating conditions using different methodologies. However, post-stress measurement conditions were kept identical to the pre-stress measurements. The
degradation in gate voltage was also measured. All stress experiments were performed during front channel operation. The
back gate was always grounded during stress.
Pre-stress and post-stress measurements were made using ac
small-signal technique. To characterize the ac analysis behavior
of a MOSFET, a small-signal model is useful. We know that
dynamic floating-body effects are of concern in digital applications [26], where they produce the hysteresis/history effect,
so it becomes necessary to analyze the small-signal behavior
of devices for analog applications. Therefore, it becomes important to undertake the reliability measurements also using the
small-signal model. Small-signal ac (pre-stress and post-stress)
measurements were done using an HP 4284A LCR meter. The
frequency of the small signal was 10 kHz at the signal level of
10 mV. Fig. 3 shows the experimental setup for the measurement
. The experiment was carried out using GPIB control via
of
a computer.
Two sets of measurements were taken for the comparison of
CON with SH SOI MOSFETs as mentioned above. First, virgin
129
Fig. 3. Experimental setup for GPIB controlled small-signal (pre-stress
and post-stress) characterization of SOI MOSFET. This setup is used for the
measurement of dynamic transconductance g . HP (high potential) and HC
(high current) terminals of LCR meter are connected to the terminal of interest
(here, gate), and LP (low potential) and LC (low current) are connected to
source for both the configurations, which assumes that LP and LC are at virtual
ground, thus, always keeping the source at ground potential. To increase the
efficiency of the measurement and to reduce the errors due to parasitics, the
four terminals, HP, HC, LP, and LC, were taken right up to the probes.
Fig. 4. Transconductance degradation for CON and SH nMOSFETs after
= 4 V, V
= V + 0:5 V,
CHC stress, Stress time = 20 000 s at V
L = 0:2 m, T = 50 nm, Tilt (SH) = 15 . The measurement was done
at small signal for V = 10 mV and f = 10 kHz.
CON and SH MOSFET were stressed for a long time of 20 000
V and
V. Measurements were
s at
taken only at the start and at the end of 20 000 s and no measurements were taken in between so as to avoid frequent interruption. The pre-stress and post-stress small-signal transconductance is shown in Fig. 4. As can be observed, the degradation
is very small in SH as compared to CON SOI MOSFET.
in
Fig. 5 shows the degradation in drain current for the same devices. It can be seen that linear as well as saturation current is
degraded heavily in CON as compared to SH device.
Experiments were performed to see the degradation of different parameters as a function of stress time. The devices were
V and at
stressed under dc stress conditions at
V. The drain current shift
obtained in a
single device will appear as a current shift in an analog circuit
[27]. Fig. 6 shows the shift in the saturation drain current meaof 0.2 V for both CON and SH SOI
sured at fixed
MOSFETs. Under identical stress conditions it can be observed
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130
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
Fig. 5. Degradation in the drain current after a dc stress of 20 000 s,
V
: V for SH and CON SOI nMOSFETs.
measurement at V
0
=02
Fig. 8. Time evolution in transconductance degradation under dc stress
conditions. Transconductance was measured at V
: V and V
V
to produce the same pre-stress current. The measurement was done at small
mV and f
kHz.
signal for V
=07
= 10
=
+
= 10
Fig. 6. Time evolution in saturation drain current degradation under dc stress
: V and V
V
conditions. Drain current was measured at V
: V.
02
= 07
=
+
Fig. 9. Time evolution in output conductance degradation under dc
:
V and
stress conditions. Output resistance was measured at V
V
V
: V.
=
Fig. 7. Time evolution in gate voltage degradation under dc stress conditions.
Gate voltage was measured, to produce the same pre-stress current at V
: V. The measurement was done at small signal for V
mV and f
kHz.
07
10
= 10
=
=
that SH SOI MOSFET shows less degradation. Fig. 7 shows the
degradation in the gate voltage for CON and SH devices. The
V to get a
pre-stress gate voltage was measured at
current value (0.1 mA) under typical analog operating conditions. The post-stress gate voltage was measured such that the
V produced the same value of pre-stress cursame
rent (0.1 mA). It is again seen that less degradation occurs in
SH device in comparison to its CON counterpart. The inset of
Fig. 7 shows the same plot in log scale. The degradation mechanism in deep-submicron SOI MOSFETs has been explained
[28] assuming a stress-induced trapping of electrons near the
drain. The length of the zone containing occupied electron traps
and/or charged interface states is a function of stress time, and a
power-law dependence is observed for both devices. The degradation in the analog operation has been described [24] for bulk
+02
= 07
MOSFETs and has been attributed to the stress-induced shift of
the pinch-off point.
Fig. 8 shows the percentage degradation shift in the ac
small-signal transconductance. The pre-stress and post-stress
transconductance was measured in saturation at a constant value
and . The constant value of current was obtained by
of
varying the gate voltage. In case of SH devices, the shift in
transconductance is small as compared to the CON devices. For
SH devices, degradation in transconductance changes its slope
after a certain period of stress time (about 2000 s). This behavior
in transconductance has been observed for different silicon film
thicknesses and channel tilt implants, though the percentage
shift is different. The reduction in the slope of degradation
has been explained by [29] as hole trapping in pre-existing
traps at the buried oxide. Banna et al. [30] explain the same
as simultaneous hole trapping and interface state generation at
the back interface coupled to front interface. The reduction in
slope may also occur for CON devices although after longer
stress time. The overall lower reduction in transconductance
degradation can be attributed to the much lower lateral electric
fields in the SH SOI MOSFET. It has also been explained [31]
as due to the peak impact ionization of asymmetrical (here,
SH) device being located further away from the surface of
the device than in the CON nMOS device [32]. Fig. 9 shows
degradation in the output drain conductance for CON and SH
devices. The drain conductance degrades faster in CON than in
SH devices. This can also be confirmed from Fig. 5, where the
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HAKIM et al.: SUPERIOR HOT CARRIER RELIABILITY OF SINGLE HALO SOI NMOSFET IN ANALOG APPLICATIONS
131
SH SOI MOSFETs are very effective in the suppression of various hot carrier degradation compared to conventional devices
under identical stress conditions. The reasons for lower degradation are looked into from 2-D device simulations. Thus, SH SOI
MOSFETs are excellent candidates for analog and mixed-mode
applications.
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Fig. 10. Time evolution in gate voltage and transconductance degradation
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Fig. 11. Simulated lateral electric field profiles (near the drain junction), along
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=
Najeeb-ud-din Hakim received the B.E. degree in
electronics and communications engineering from
the Kashmir University, India, in 1985, the M.Eng.
degree in solid-state electronics from the University
of Roorkee, India, and the Ph.D. degree from the
Indian Institute of Technology (IIT), Bombay, India,
in 2003.
He is currently a faculty member in the Department
of Electronics and Communication Engineering, National Institute of Technology, Srinagar, India. His research interests are in the field of SOI, CMOS devices, design, and technology, and CMOS in mixed-signal applications.
V. Ramgopal Rao (M’98–SM’02) received the
M.Tech. degree from the Indian Institute of Technology (IIT), Bombay, India, in 1991, and the
Dr.-Ing. degree (magna cum laude) from the Faculty
of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany, in 1997. His doctoral
thesis was on planar-doped-barrier sub-100-nm
channel length MOSFETs.
He was a Deutscher Akademischer Austauschdienst (DAAD) Fellow from 1994 to 1996 and from
February 1997 to July 1998 and in 2001, a Visiting
Scholar with the Department of Electrical Engineering, University of California,
Los Angeles. He is currently an Associate Professor in the Department of Electrical Engineering, IIT, Bombay. His areas of interest include physics, technology and characterization of short-channel MOSFETs, CMOS scaling for
mixed-signal applications, and bio-MEMS. He has over 120 publications in
these areas in refereed international journals and conference proceedings and
holds patents in these areas.
Dr. Rao is an organizing committee member for various international conferences held in India. He is a Fellow of IETE and is currently the Chairman of the
IEEE AP/ED Bombay Chapter.
Juzer Vasi (M’73–SM’96) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology (IIT), Bombay, India, in 1969 and
the Ph.D. degree from The Johns Hopkins University,
Baltimore, MD, in 1973.
He taught at The Johns Hopkins University and
the IIT, Delhi, before moving to the IIT, Bombay,
in 1981, where he is currently a Professor. He was
Head of the Electrical Engineering Department from
1992 to 1994. His research interests are in the area
of CMOS devices, technology, and design. He has
worked on MOS insulators, radiation effects in MOS devices, degradation and
reliability of MOS devices, and modeling and simulation of MOS devices.
Dr. Vasi is a Fellow of IETE, a Fellow of the Indian National Academy of Engineering, and a Distinguished Lecturer of the IEEE Electron Devices Society.
Jason C. S. Woo (SM’97) received the B.A.Sc.
(honors) degree in engineering science from the
University of Toronto, Toronto, ON, Canada, in
1981, and the M.S. and Ph.D. degrees in electrical
engineering from Stanford University, Stanford, CA,
in 1982 and 1987, respectively.
He joined the Department of Electrical Engineering, University of California, Los Angeles, in
1987, where he is currently a Professor. He received
a Faculty Development Award from IBM from 1987
to 1989. He has done work on low-temperature
devices for VLSI and space applications, SOI BiCMOS, and GeSi BiCMOS.
Significant achievements include the analysis and fabrication of cryogenic
bipolar transistors, the identification of hot-carrier reliability failure modes at
reduced temperatures, the first demonstration of GeSi quantum-well MOSFETs, and the investigation of device physics/technology for deep submicron
SOI CMOS. He has also worked on technology such as drain engineering and
alternative gate dielectrics to improve CMOS performance and reliability. He
has authored or coauthored over 150 papers in technical journals and refereed
conference proceedings in these areas. His research interests are in the physics
and technology of novel device and device modeling.
Dr. Woo served on the IEEE IEDM Program in 1992 and was the Publicity
Chairman in 1993. He has served on the technical committee of the VLSI Technology Symposium since 1992 and is currently the Secretary for the conference. Since 1993, he has been on the IEEE SOI Conference Committee and was
the Technical Program Chairman for the conference in 1999 and the General
Chairman in 2000.
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