542
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 47, NO. 3, JUNE 2000
A Novel High-Power Low-Distortion Synchronous
Link Converter-Based Load Compensator Without
the Requirement of Var Calculator
Kishore Chatterjee, B. G. Fernandes, and Gopal K. Dubey, Senior Member, IEEE
Abstract—A high-power low-distortion static var compensator based on a synchronous link converter has been
proposed, where the harmonics are eliminated by incorporating
a low-power insulated-gate-bipolar-transistor-based controlled
current auxiliary converter in conjunction with a high-power
gate-turn-off-thyristor-based converter. In this paper, a new
load compensator based on this topology is proposed which does
not require the information of the voltampere required by the
load. As the requirement of the reactive voltampere calculator is
eliminated, the scheme becomes insensitive to system frequency
variations, temperature, and component aging. The control
scheme required for the compensator is developed. The operation
of the scheme is validated through extensive simulation studies.
Experimental results obtained from a laboratory prototype are
provided to demonstrate the viability of the scheme.
Index Terms—Harmonic elimination, load compensation, synchronous link converter var compensator, static var compensator,
var calculatorless operation.
I. INTRODUCTION
T
HE traditional methods of reactive voltampere compensation consisting of switched capacitor or fixed capacitor
and phase-controlled reactor coupled with passive filters are
increasingly being replaced by new approaches utilizing the
concept of synchronous link converters [3]. This new class
of compensators, which has earned overwhelming response
from the researchers, is known by several terminologies,
such as the “var generator” [4], “advanced static var generator” [5], “synchronous solid-state var compensator” [6],
“pulsewidth modulation (PWM) inverter var compensator”
[7], “STATCON,” etc. In this paper, it is referred to as a
synchronous link converter var compensator (SLCVC). A new
technique of harmonic elimination for the SLCVC is proposed
in [1] and [2], wherein low-frequency high-power devices and
high-frequency low-power devices are combined to extract
superior performance. The basic philosophy of the scheme
is that two converters sharing a common dc bus are used in
parallel, of which one is realized by gate-turn-off thyristors
(GTO’s), while the other one is realized by insulated gate
bipolar transistors (IGBT’s). The blocking voltage rating of
Manuscript received December 16, 1998; revised August 31, 1999. Abstract
published on the Internet March 12, 2000.
K. Chatterjee and B. G. Fernandes are with the Department of Electrical
Engineering, Indian Institute of Technology, Bombay 400076, India (e-mail:
kishore@ee.iitb.ernet.in; bgf@ee.iitb.ernet.in).
G. K. Dubey is with the Department of Electrical Engineering, Indian Institute
of Technology, Kanpur 208016, India (e-mail: gdubey@iitk.ac.in).
Publisher Item Identifier S 0278-0046(00)04742-0.
IGBT’s and GTO’s of the auxiliary and the main converter,
respectively, is the same and is decided by the dc-link voltage.
Although IGBT’s having forward-blocking voltage capability
of 4.5 kV are commercially available, they cannot be switched
at high frequency while negotiating high current. This is
mainly due to the constraint imposed by the long current
tail associated with the device characteristic. Therefore, all
high-power converters realized either by GTO’s or IGBT’s
should be operated at low switching frequency. The GTO
converter (or the main converter) is operated with PWM control
based on selective harmonic elimination technique so that only
few low-order harmonics are eliminated. The high-frequency
parallel or auxiliary converter is operated in the controlled
current mode to eliminate the next higher order harmonics
generated by the main compensator, as a result of which its
voltampere rating remains low. When var compensators are
used for load compensation, the load var demand is sensed
by a reactive voltampere calculator (RVAC) based on which
the compensator generates the required var. These RVAC’s
are sensitive to system frequency variations, temperature rise,
and component aging. As a result, the compensation process
is not accurate [8]. Moreover, the addition of an involved
circuitry utilizing high-precision components, coupled with the
requirement of frequent tuning of the circuit, makes the overall
process complicated and costly.
In order to eliminate the requirement of the RVAC, a novel
control technique is proposed in this paper. The underlying philosophy of the proposed technique can be stated as follows:
in the SLCVC’s proposed in [6] and [7], the auxiliary compensator current is minimum if the entire var demand of the
load is supplied by the main compensator. The var supplied
by the main compensator depends on the magnitude of reference dc-link voltage Vdc(rf ) . An incorrect value of Vdc(rf ) will
result in the auxiliary compensator supplying var to the load,
which, in turn, increases its current. Thus, by monitoring the
auxiliary compensator current, a suitable value for the reference
dc-link voltage can be set so that the auxiliary compensator current is minimum. Since this current is the control variable of the
closed-loop control structure which determines Vdc(rf ) , variations in system frequency and parameters do not have any effect on the compensation process. The control scheme is applied
for single-phase and three-phase systems. Detailed simulation
studies and the experimental results obtained from a laboratory
prototype are provided.
A modified version of the above scheme incorporating
a current limit feature in the auxiliary compensator is
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CHATTERJEE et al.: SYNCHRONOUS LINK CONVERTER-BASED LOAD COMPENSATOR
543
Fig. 1. Power circuit configuration.
Fig. 3. Internal block diagram of RDG
TABLE I
TRUTH TABLE FOR REALIZATION OF RDG
(a)
(b)
Fig. 2.
Possible intersections of templates and auxiliary compensator current.
also investigated. The effectiveness of this modified scheme is
demonstrated through simulation studies.
II. OPERATING PRINCIPLE
The power circuit configuration of the scheme is shown
in Fig. 1. The main converter is operated with selective harmonic elimination technique, so as to eliminate 5th, 7th, and
11th harmonics. Hence, the switching frequency of the main
compensator devices is 450 Hz. The fundamental component
of the main compensator current is controlled by controlling
the magnitude of dc-link voltage. Three reference sinusoids
irf (a) , irf (b) , and irf (c) having equal amplitude Irf and in
phase with the line-to-neutral voltages vs(a) , vs(b) , and vs(c)
are synthesized. The source currents are sensed and compared
with the respective reference sinusoids. The error thus obtained
decides the switching pattern of the auxiliary converter devices
so that source currents are made to follow the respective
reference current within a hysteresis band. As the source
currents are forced to follow sinusoidal references, the load
harmonics, if present, also are eliminated. The reference dc-link
voltage Vdc(rf ) is set by monitoring the auxiliary compensator
current icx . However, the magnitude of icx contains only
the information regarding the amount of var handled by the
auxiliary compensator. For determining Vdc(rf) , in addition to
the magnitude of var, the sign (lag or lead) of the var handled
is also required. Suppose that, at any instant of time, it is
found that icx is more than some prescribed limit. This implies
that the auxiliary compensator is supplying either lagging or
leading var. If it supplies lagging var, the reference dc-link
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Fig. 4.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 47, NO. 3, JUNE 2000
Control block diagram of the scheme.
Fig. 5. Transient behavior for a change in load from (1:67 + j 6:9)KVA to (1:67 + j 17:0)KVA. (a) DC-link voltage and reference dc-link voltage. (b) Source
voltage and source current. (c) Auxiliary compensator current and main compensator current. (d) Load current.
voltage has to be increased, otherwise, it has to be decreased.
The sign of the var handled by the auxiliary compensator is
determined as follows. For this purpose, four current templates
C1 , C2 , C3 , and C4 are synthesized. Template C1 is obtained
by adding a dc bias of magnitude DCb to a square wave
having an amplitude of Tp and phase shifted by 90 from the
utility voltage Vs . The dc bias DCb determines the maximum
allowable auxiliary compensator current at steady state. The
value of Tp is so chosen that it is always higher than the peak
of icx for all operating conditions. Template C2 is generated by
adding a dc bias of 0(Tp + 2DCb) to C1 . Templates C3 and
C4 are synthesized by inverting the square wave that produces
C1 and C2, and by adding necessary dc biases to it. The four
current templates are shown in Fig. 2. The compensator current
icx is simultaneously compared with the four templates C1 –C4 .
Two cases of auxiliary compensator current: 1) icx1 , auxiliary
compensator is supplying lagging var, and 2) icx2 , auxiliary
compensator is supplying leading var, are considered. The
possible intersections of icx1 and icx2 with the four templates
are shown in Fig. 2. The interpretations of the error signals
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CHATTERJEE et al.: SYNCHRONOUS LINK CONVERTER-BASED LOAD COMPENSATOR
545
Fig. 6. Transient behavior for a change in load from (1:67 + j 6:9) KVA/phase to (1:67 + j 17:0) KVA/phase. (a) DC-link voltage and reference dc-link voltage.
(b) Phase-A source voltage and source current. (c) Phase-A auxiliary compensator current and main compensator current. (d) Phase-A, phase-B, and phase-C
auxiliary compensator currents.
Fig. 7. Transient behavior for a change in load from (1:67 + j 6:9) KVA/phase to (1:67 + j 17:0) KVA/phase (modified control). (a) DC-link voltage and
reference dc link voltage. (b) Phase-A source voltage and source current. (c) Phase-A auxiliary compensator current and main compensator current. (d) Phase-A,
phase-B, and phase-C auxiliary compensator currents.
obtained from the comparisons are enumerated in Table I and
this table is used to realize the reference dc-link voltage generator circuit (RDG). The internal block diagram of the RDG
is shown in Fig. 3. The negative clippers are required to accomplish entries 2 and 3, while positive clippers are required
to accomplish entries 6 and 7 of Table I. The error (err) thus
obtained contains a dominant second harmonic component
in addition to the dc component. This harmonic components
are eliminated using a low-pass filter. The filtered error is
processed by the proportional–integral (PI) controller which
sets Vdc(rf) . The limiter ensures that, during the transient
period, Vdc(rf ) does not fall below the magnitude of the peak
utility voltage or rise above the maximum value of Vdc for
which the compensator is designed.
For the three-phase case, three sets of templates
corresponding to the three phase voltages are synthesized. Each set of templates is then compared with
the auxiliary compensator current of the respective phase.
The three sets of error thus obtained are added and processed
by the PI controller which sets Vdc(rf) .
A. Control Configuration
The control block diagram of the scheme is shown in Fig. 4.
The auxiliary compensator current icx is sensed and fed to the
RDG which generates Vdc(rf) (switch S in position SW1). The
dc-link voltage is filtered and compared with Vdc(rf) . The error
being processed by the PI-CONT. (1) is used to control so that
requisite amount of real power is drawn from or supplied to the
utility to change Vdc(rf ) . The output of the PI-CONT. (2) sets
the magnitude of the reference current Irf . Thus, any change
in Vdc(rf) due to change in load var results in a simultaneous
change in and Irf , leading to an increase in the dc-link voltage.
A small-signal model of the scheme, along with stability analysis, is provided in [9].
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546
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 47, NO. 3, JUNE 2000
Fig. 8. Transient behavior of single-phase SLCVC. TR1: dc-link voltage
(30V/div); TR2: reference dc-link voltage (30V/div); TR3: auxiliary
compensator current (4A/div); TR4: load current (10A/div). Time scale:
0.1s/div.
Fig. 10. Transient behavior of three-phase SLCVC. TR1: dc-link voltage
(30V/div); TR2: reference dc-link voltage (30V/div); TR3: auxiliary
compensator current (2A/div). Time scale: 0.1s/div.
Fig. 9. Transient behavior of single-phase SLCVC. TR1: dc-link voltage
(30V/div); TR2: reference dc-link voltage (30V/div); TR3: auxiliary
compensator current (4A/div); TR4: load current (10A/div). Time scale:
0.1s/div.
Fig. 11. Transient behavior of three-phase SLCVC. TR1: dc-link voltage
(30V/div). TR2: reference dc-link voltage (30V/div); TR3: unfiltered error
signal (err) obtained from the point preceding to the filter of rdg. Time scale:
0.1s/div.
III. SIMULATION STUDIES
To verify the operation of the proposed control method,
detailed simulation studies are carried out for single-phase and
three-phase systems. The system parameters chosen for the
purpose of simulation are: Lm = 20 mH, La = 12 mH, and
dc-link capacitance C = 2000 F. The parameter DCb is set at
35.0 A. The system voltage is taken to be 230 V for single phase,
and that for three phase is 400 V. The behavior of the single-phase
compensator for a step change in load from (1:67 + j 6:9)
KVA to (1:67 + j 17:0) KVA is shown in Fig. 5.The source
current is always maintained in phase with the utility voltage,
which implies that the compensator is fully compensating the
reactive voltampere demand of the load. The losses taking
place within the compensator are roughly proportional to the
current handled by the compensator. Thus, the increment in
the load reactive voltampere demand increases the converter
losses. In order to compensate these losses, the converter draws
a higher value of real component of current from the source.
This results in the increment of the utility current, even though
there is no increment in the real component of the load. In the
simulation studies, as the change in the reactive voltampere
demand of the load is almost 145%, this change in the source
current is perceptible.
The same set of inductors and a capacitor of 400 F are
used for the three-phase case. The value of DCb remains 35.0.
The response of the compensator for a step change in load
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CHATTERJEE et al.: SYNCHRONOUS LINK CONVERTER-BASED LOAD COMPENSATOR
from (1:67 + j 6:9) KVA/phase to (1:67 + j 17:0) KVA/phase
is shown in Fig. 6.
It can be seen from the simulated waveforms that the auxiliary
compensator current increases during the transient period. As
the short time current rating of the devices is around twice
that of their continuous rating, an increase in the magnitude of
current through the auxiliary compensator devices during the
short transient period is permissible. However, for applications
where a large change in the magnitude of var is expected,
the magnitude of current through the auxiliary compensator
devices has to be limited during the transient period. This is
achieved by incorporating a slight modification in the control
structure, which is discussed in the next section.
IV. MODIFIED CONTROL STRATEGY
The RDG takes action only when jicx j exceeds DCb . Two
current limits 6Icx(max) are set, and when icx is within these
two limits, the auxiliary compensator is operated as explained
previously, and, if icx > Icx(max) or icx < 0Icx(max) , gating
pulses to the auxiliary compensator devices are disabled. As a
result, icx will either fall or rise toward zero. When icx crosses
(Icx(max) 0 h) or (0Icx(max) + h), gating pulses are released
again. Thus, during the transient period, when jicxj tries to
increase beyond one of the set limits, it is effectively being
trimmed and maintained at that limit within a hysteresis band
h. The parameters jIcx(max) j and h are chosen to be 40.0 and
5.0 A, respectively. Simulated waveforms for the three-phase
SLCVC for a change in load from (1:67 + j 6:9) KVA/phase to
(1:67 + j 17:0) KVA/phase are shown in Fig. 7.
V. EXPERIMENTAL RESULTS
Experimental studies are carried out to validate the operation
of the proposed technique and results obtained from the laboratory prototype are presented.
The oscillogram record depicting the transient behavior of
the scheme for a step change in load current from (0:5 + j 0:5)
to (0:5 + j 6:0) A is shown in Fig. 8. Initially, this increased
reactive component of the load current is being supplied by the
auxiliary compensator which causes the RDG to increase the
reference dc-link voltage. As the dc-link voltage increases, the
auxiliary compensator current decreases and, eventually, steady
state is reached when it falls below DCb . A similar oscillogram
record for a step change in load current from (0:5 + j 6:0) to
(0:5 + j 0:5) A is shown in Fig. 9.
In the three-phase case, the load current is maintained at
(0:5 + j 6:0) A/phase and Vdc(rf ) is initially set at 150 V by
keeping the switch S of Fig. 4 in position SW2. This value
is deliberately kept less than the value required for the main
compensator to be able to fully compensate the load. The
control action is initiated by changing the switch position from
SW2 to SW1. The oscillogram records depicting the behavior
of the compensator are shown in Figs. 10 and 11. Prior to the
changing of the switch position, the auxiliary compensator
is supplying lagging var, since 150 V is inadequate for the
main compensator to fully compensate the load. Hence, the
magnitude of the auxiliary compensator current is higher than
DCb . When the switch position is changed, in order to reduce
547
the auxiliary compensator current, the RDG increases Vdc(rf ) .
This change in reference voltage, increases Irf and . When
the magnitude of the dc-link voltage becomes higher than that
required for the main compensator to fully compensate the
load, the auxiliary compensator will start supplying leading
var. Steady state is reached when the auxiliary compensator
current falls below DCb .
VI. CONCLUSIONS
A novel control strategy for high-power SLCVC’s involved in
load compensation has been proposed. The proposed technique
eliminates the requirement of the reactive voltampere calculator. This improves the system reliability. Moreover, the compensation process is insensitive to system parameter variations,
thereby enhancing its accuracy. The effectiveness of the scheme
was examined through detailed simulation and experimentation.
A modified control principle which limits the auxiliary compensator current during the transient period was also proposed.
REFERENCES
[1] K. Chatterjee, B. G. Fernandes, and G. K. Dubey, “A novel high power
self-commutated static var compensator for load compensation,” in
Proc. IEEE PEDES’97, Singapore, 1997, pp. 65–71.
, “A simplified control strategy for a high power low distortion syn[2]
chronous link converter var compensator,” in Proc. IEEE PEDES’98,
Perth, Australia, 1998, pp. 330–335.
[3] V. R. Kanetkar, M. S. Dawande, and G. K. Dubey, “Recent advances in
synchronous link converters,” in Power Electronics and Drives, G. K.
Dubey and C. R. Kasarbada, Eds. New Delhi, India: IETE, 1994.
[4] L. Gyugi, “Reactive power generation and control by thyristor circuits,”
IEEE Trans. Ind. Applicat., vol. IA-15, pp. 521–532, Sept./Oct. 1979.
[5] C. W. Edwards, K. E. Mattern, E. J. Stacey, P. R. Nannery, and J. Gubernick, “Advanced static var generator employing GTO thyristors,” IEEE
Trans. Power Delivery, vol. 3, pp. 1622–1627, Oct. 1988.
[6] L. T. Moran, P. D. Ziogas, and G. Joos, “Analysis and design of a threephase synchronous solid-state var compensator,” IEEE Trans. Ind. Applicat., vol. 25, pp. 598–608, July/Aug. 1989.
[7] G. Joos, L. T. Moran, and P. D. Ziogas, “Performance analysis of a PWM
inverter VAR compensator,” IEEE Trans. Power Electron., vol. 6, pp.
380–391, July 1991.
[8] T. S. Tepper, J. W. Dixon, G. Venegas, and L. Moran, “A simple frequency-independent method for calculating the reactive and harmonic
current in a nonlinear load,” IEEE Trans. Ind. Electron., vol. 43, pp.
647–653, Dec. 1996.
[9] K. Chatterjee, “Synchronous link converter var compensators and active
power filters,” Ph.D. dissertation, Dep. Elect. Eng., Indian Inst. Technol.,
Kanpur, India, 1998.
Kishore Chatterjee was born in Calcutta, India, in
1967. He received the B.E. degree from Regional
Engineering College, Bhopal, India, the M.E.
(power electronics) degree from Bengal Engineering
College, Calcutta University, Calcutta, India, and the
Ph.D. degree in power electronics from the Indian
Institute of Technology, Kanpur, India, in 1990,
1992, and 1998, respectively.
From 1997 to 1998, he was a Senior Project Associate at the Indian Institute of Technology, Kanpur,
India, where he was involved in a project on powerfactor correction and active power filtering, which was sponsored by the Central Board of Irrigation and Power, India. Since December 1998, he has been
an Assistant Professor in the Department of Electrical Engineering, Indian Institute of Technology, Bombay, India. His current research interests are modern
var compensators, active power filters, utility-friendly converter topologies, and
electronic ballast.
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548
B. G. Fernandes was born in Mangalore, India, in
1962. He received the B.Tech. degree from Mysore
University, Mysore, India, the M.Tech. degree from
the Indian Institute of Technology, Kharagpur, India,
and the Ph.D. degree from the Indian Institute of
Technology, Bombay, India, in 1984, 1989, and
1993, respectively.
He was with M/S Development Consultant Ltd.
from 1985 to 1987. From 1993 to 1997, he was
with the Department of Electrical Engineering,
Indian Institute of Technology, Kanpur, India, as
an Assistant Professor. He is currently with the Department of Electrical
Engineering, Indian Institute of Technology, Bombay, India. His current
research interests are PMSM drives, vector-controlled drives, quasi-resonant
link converter topologies, modern var compensators, and active power filters.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 47, NO. 3, JUNE 2000
Gopal K. Dubey (SM’83) was born in 1939. He received the B.E. (Hons.) degree from Jabalpur University, Jabalpur, India, and the M.Tech. (drives and controls) and Ph.D. degrees from the Indian Institute of
Technology, Bombay, India, in 1963, 1965, and 1972,
respectively.
He was an Assistant Professor at the Indian
Institute of Technology, Bombay, India, until 1977.
He has been a Professor at the Indian Institute of
Technology, Kanpur, India, since 1978. He was an
Honorary Visiting Research Fellow and Commonwealth Scholar at the University of Bradford, Bradford, U.K., from 1974 to
1975 and a Visiting Professor at the University of British Columbia, Vancouver,
BC, Canada, from 1983 to 1984 and at Virginia Polytechnic Institute and State
University, Blacksburg, from 1984 to 1985. He was a Senior Visiting Fellow
at the National University of Singapore in 1995. His fields of interest include
electrical drives, power electronics, control systems, and engineering education.
He is the author of Power Semiconductor Controlled Drives (Englewood Cliffs,
NJ: Prentice-Hall, 1989), Thyristorized Power Controllers (New Delhi, India:
Wiley Eastern, 1986), and Fundamentals of Electrical Drives (New Delhi,
India: Narosa, 1994). He edited Power Electronics and Drives, (New Delhi:
Tata-McGraw Hill, 1993) and has authored 150 published research papers. He
is an Honorary Editor of the IETE Journal of Research.
Dr. Dubey received the Bimal Bose Award from the Institute of Electronics
and Telecommunication Engineers (IETE) in 1990 for excellence in power electronics. He is a Fellow of the IETE, Institution of Engineers, and Indian National Academy of Engineering. He was Chairman of the IEEE UP Subsection and then Section during 1989–1993. He is an Associate Editor of the IEEE
TRANSACTIONS ON POWER ELECTRONICS.
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