6-bit Low-power Subranging-ADC With Increased
Throughput
Maryam Shojaei Baghini, Senior Member, IEEE
Santhosh Kumar Gowdhaman
Department of Electrical Engineering
Indian Institute of Technology Bombay
India 400076
Email: mailgsk@ee.iitb.ac.in
Department of Electrical Engineering
Indian Institute of Technology Bombay
India 400076
Email: mshojaei@ee.iitb.ac.in
Abstract- This paper describes a high-speed low-power sub­
ranging Flash ADC designed in 90nm Mixed-Mode CMOS
process. The maximum speed of subranging-ADC is limited by
the time taken for the fine-ADC reference to settle. The proposed
method splits optimally the total time taken for the coarse-ADC
and fine-ADC comparisons to achieve the maximum possible
clock speed. An auxiliary track-and-hold has been used in the
interleaved track-and-hold to introduce 1/2 clock-cycle delay.
Yin
Simulations results show that the subranging-ADC achieves
SFDR of 37.7 dB at sampling rate of 1.54GS/s for 360MHz input
and dissipates 15 mW power from I-V supply. It has 4.6 ENOB
@ Nyquist and FoM of 0.4 pJ/conv. step. Minimum-size devices
have been used in the comparator to achieve low-power. A digital
b2
offset calibration method has been used to reduce the offset of
bl
comparators.
bO
I.
INTRO DUCTION
High speed medium resolution analog-to-digital converters
(ADCs) are essential in many applications such as data storage
read channels and wireless communication systems. Fully
parallel flash architecture requires 2N - 1 comparators and
hence comsumes large power. The number of comparators
can be reduced using folding or subranging flash architecture.
However the maximum input frequency of folding flash ADC
is limited to 100 MHz [ 1] due to increased distortion at high
input frequencies [2]. Different techniques for subranging­
ADC have been reported in [3]-[6]. In [6], one coarse-ADC
(CADC) and two time-interleaved fine-ADCs (FADCs) are
used to increase the throughput of subranging ADe. In one
aproach [3] latency of subranging ADC has been decreased by
using a TIH circuit to precharge Vref (reference voltage) levels
of FADC, hence decreasing settling time of Vref in fine ADe.
Reference [4] uses a single CADC and a single fine ADC
with interleaved track-and-hold to increase the throughput.
Fully flash ADC at very high sampling rate of 3.5 aS/s has
been reported [7]. However throughput of reported subranging
ADCs is limited to 1 aS/s [8]. We have devised a technique
to increase the throughput to 1.5 aS/s as explained in detail
in section III of this paper.
II.
CONVENTIONAL SU BR ANGING ARCHITECTURE
Fig. 1 shows architecture of conventional subranging flash
ADC with interleaved track-and-hold. Conventional subrang­
ing flash ADC consists of a CADC and a FADe. First the
978- 1-4244-7773-9/ 10/$26.00 ©20 10 IEEE
Fig.
l.
Block diagram of subranging ADC with interleaved track-and-hold
I
TH I
Coone
Comparator
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Fln.
Fig. 2.
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S(N)
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S(N+I)
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:
:
:
V
IV
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H(N+l)
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CCN+I
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C(N-
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:
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X
C(N
X
RST X
I
Vll
S(N+3)
I
'("RSr
.- X
H(N +!)
H(N+l)
:
)X
X
I
S(N+l)
:H CNl
I
S(N+:!)
S(N+3)
CCN+I
X
RSf
I
X
Timing diagram of subranging ADC with interleaved track-and-hold
CADC performs quatization of sampled input and gives the
thermometer code. The thermometer-to-binary encoder (ENC)
gives the MSB bits. Depending on the CADC output, corre­
sponding subrange of reference bank is selected by the switch
matrix. The the FADC performs quantization of the input
and gives the LSB bits. In subranging ADC architecture long
settling time is required for switching the reference of Fine
ADC [3]. Hence time taken by the Fine ADC for resolving
the input is much longer than that of the coarse ADe. This
limits the speed of subranging architecture.
497
,
,
-'
,
-,
,
,
,
taken for Vref-FADC to align is introduced within half clock
period between the falling edge of CADC comparator and the
next rising of the FADC comparator clock. This increases the
minimum clock-period Tck.
Buffer
,
,
FADC-R.o£
Tck
CADC
2 = txor + tbuffer + tref-settle + tsu
Mnxin:auJU delay path
In the proposed method, a half clock-cycle delay is introduced
in the interleaved track-and-hold path so that this total delay
is accommodated in one clock period. This allows to have
shorter Tck.
aralor out ut
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( 11. + 1)
0
CAoe output
III.
Changes
o
i
o
hall· clock cycle
j.
CADC
cOlTlparator clock
goes high
FADC
cOlTlparator clock
goes high
Fig. 3.
Vref-FADC alignment time in conventional architecture
Fig. 2 shows the timing diagram of ADC with interleaving
track-and-hold [4]. Once the CADC track-and-hold holds the
data at the input of CADC comparator array, the comparator
clock goes high after a setup time delay of tsu so that input
is settled when comparator is latched. When the comparator
clock goes high, comparator resolves the input and the output
is latched when clock goes low. The reference select logic
and the delay of each component is shown in Fig. 3. The
logic consists of an XOR, buffer and transmission-gate of the
switch-matrix. Trasmission-gate switch selects the appropriate
voltage-reference Vref-FADC for FADe. The comparator ar­
ray gives the thermometer code. Adjacent comparator-outputs
are connected to XOR gate array. Only one of the XOR­
outputs goes high, and the corresponding reference bank of
FADC is selected. The delay from output of CADC comparator
to clock of FADC comparator is the time taken for the FADC
reference to settle which is given as :
delay
= txor + tbuffer + tref-settle + tsu
(2)
The timing diagram of the proposed subranging-ADC is
shown in Fig. 4. In the proposed method, latch in the
CADC comparator has been replaced by Flip-Flop so that
the output transition occurs always after the falling edge
with clock-to-Q delay tck-Q. This removes the uncertainty
associated with comparator output-transition instant caused
by the variable magnitude of differential-input. The FADC
comparator comparison is delayed with respect to CADC
comparator comparison by 1.5 Tck to have one clock period
between falling edge of CADC clock and rising edge of FADC
clock. Thus the time available for the Vref-FADC to settle is
Tck as shown in Fig. 5 unlike It in conventional method.
This allows to increase the clock-frequency. The analog input
arriving at the FADC has to be delayed by additional half­
clock cycle.
I
THI/THl
TH3a
TH4a
, X
Fl",
Comparator
RSf
"'!
H(N-I)
H(N S(N-I)
X
1111
n
:H(N)
S(N )
TH3b
TH4b
i
·
S(N)
Coarse
Comparato
( 1)
where txor, tbuffer, tref-settle and tsu are the delays of XOR,
buffer to drive the transmission-gate, settling time of reference
and setup time for the comparator respectively. The delay of
buffer depends upon the fanout and tref-settle is O.69xNxT
where T is time constant of the transmission gate switch and
N is the required bit accuracy. Once the CADC comparator
output changes, Vref-FADC starts to change after a delay
of tXOR + tinv + tbuffer and settles after additional time of
tref-settle·
However, in conventional architecture the CADC compara­
tor output transition occurs during the transparent phase of the
latch when the clock is high. If the input difference is small,
the output transition takes longer time and occurs just before
the falling edge of clock and when input difference is large,
the output transition occurs immediately after the rising edge
of clock. Therefore, when input difference is small, the time
PROPOSED METHOD
C(N -2
Fig. 4.
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N
( )
:
: RSf
:
I
I
X
:
I
C(N-I
I
S(N+2)
X
RSf
S(N+J)
5(N+2)
H ( +2)
X
I
RST
X
I
C(N)
I
RSf
S(N+3)
I
I
S(N+t)
X
VlI
I
X C(N+2) X
H(N)
I
VI
HN
( +2)
RSf
HN+l)
X
\I(N-I)
RSf
CN
( +I
RSf
( + )
:SN
I X
: SN
e )
v
IV
HN
( +l)
X
�RSf
C(N )
:
:
X:
I
( +ll
: SN
X
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RST
H(N+l)
X
RSf
X
C(N+'
X
Timing diagram of proposed scheme
IV.
CIRCUIT DESIGN
The block diagram of proposed method is shown in Fig.
6. The entire ADC has been designed in UMC 90nm Mixed­
Mode CMOS process. It consists of single CADC and FADe.
TH 1 and TH2 operate on the same clock. Two pairs of in­
terleaved track-and-hold circuits TH3a-and-TH4a, and TH3b­
and-TH4b operate on clocks of 25 % duty cycle. TH 1 tracks the
input and holds it on capacitor Cmain' THI and TH2 operate
on the same clock. During hold-phase of TH2, it holds the
input at CADC input while the TH3a or TH4a transfers the
input from Cmain to Caux. During the next clock-cycle the
input is transfered from Caux to the input of FADC via TH3b
498
B.
Transmission gate based track-and-hold has been used, with
dummy switches to reduce the effect of charge injected during
falling edge of clock. Track-and-hold with bootstrap-switch is
not required since the bottle neck for subranging architecture
is the reference settling time of FADC and not the track­
and-hold. Also transmission gate based switch requires less
power compared to bootstrap switch. Two CADC track-and­
hold circuits THl and TH2 which operate on same clock are
connected in series . The associated time constant is given by
Elmore model as :
(n+l)
i
I
one clock cycle
. -------=-=-=--=-=-=-=--=-=------=
CADC
comparator clock
goes low
Fig. 5.
Track-and-Hold
t
FADC
comparator clock
goes high
'Tnet
Vref-FADC alignment-time in proposed architecture
= ronTHl,(Cmain + CinCADC) +ronTH2,CinCADC
(3)
Let, Cmain/ CinCADC
k. Size of THI is chosen k times
large as TH2 such that the
=
or TH4b. Seperate reference ladders for CADC and FADC
have been used here.
C�I'T
V,m
Fig. 6.
'Tnet
(4)
The analog input held in Cmain is transferred to Caux1
and Caux2 by TH3a and TH4a during alternate clock cycles
respectively. The input is then applied at FADC input by TH3b
and TH4b. Caux is chosen large compared to CinFADC to
avoid charge sharing. Here, Cmain of 200 fF and Caux of
50 fF are used. Caux is discharged using reset (RST) switch
before a new input is stored. Cmain and Caux bottom plates
are connected to Vcm = 0.5V.
C.
b2
bl
b4l
1
y,) . ronTH2. CinCADC
= (2 +
Gain error correction
The gain error caused when the input is switched from
Cmain to Caux is given as Caux/(Caux + Cmain). The VrefMax
and VrefMin of FADC reference ladder are calibrated to
account for the gain error, by connecting the input terminal
to a known reference voltage.
Block Diagram of proposed subranging ADC
TABLE I
A.
PERFORMANCE COMPARISON
Comparator Design and Offset Compensation
II
Fig. 7 shows the designed comparator along with the
detailed offset compensation circuit. Fully differential archi­
tecture has been used for the comparator to increase the
input swing. The comparator consists of 5-stage preamplifier,
sense-amplifier based SR latch and D-Iatch. The positive SR
latch and negative D-Iatch form the flipflop which allows
comparator output transition only at negative edge of the clock.
PMOS active load has been used for the preamplifier instead
of resistor to save area . Minimum size devices have been used
to reduce the power consumption. However, this causes high
offset voltages at the comparator input.
A digital offset correction method using 5-bit current steer­
ing DAC (CSDAC) has been adopted here. During comparator
offset-calibration, the input terminal of each comparator is
connected to Vref' The output of comparator is given to
up-down counter which goes to CSDAC whose output is
connected to the preamplifier output nodes. CSDAC controlled
by the counter creates an offset compensation current which
nullifies the offset.
Resolution (bit)
Is
(Gsls)
[8] I
measured
[911
[7] I T his work I
measured measured
simulated
6
6
6
6
I
0. 7
3.5
1.54
42/42
47/43
44138
43/29
Pd (mW)
Vdd (V)
30
7
98
1.2/1.0
I
0.9
IS
I
FoM (pJ)
0. 8
0.25
0.95
0.4
90
90
90
90
SFDR(DClNyquist)(dB)
Technology (nm)
Architecture
subranging subranging
flash subranging
V. SIMUL ATION RESULTS
The subranging ADC, was designed using 90nm sophis­
ticated foundry model files by Cadence Spectre. Slow-Slow
comer as the worst case comer for the achieved speed is
considered. The DNL after digital offset correction has been
plotted in Fig 8. The spurious-free dynamic range (SFDR) as
a function of input frequency fin is plotted in Fig. 9. SFDR
starts from 43 dB at low input frequencies and reaches about
29 dB for Nyquist frequency. SFDR vs. sampling frequency
499
40
.
...
..
.
..
..
�.. . > ............ - : • SFDR
-...;.
F $.--.
= 1.54GHz
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...
.. ..
: ..... .... �
.
. .
.
.
.
..
O+--_-.-�--.-�-_.-��
o
400
600
200
Inpnt fre(IUency (MHz)
Fig. 9.
800
SFDR vs. input frequency
50 .----.----.-�-.----,----�
._._.� ._�
._:. ___ -·-SF D R
.. . .. . _ . .
40 . .. . .. . .. . . . .. . . .. . .. . . .. . .. . .. . .. . . .. . . .. . .. .
Fill=70MHz:""
:
:
(8)
_
•
� 30
_
I
..,.
II: 20
c
10
::;
+-
O+o
__
-
Fig. 10.
(b)
Fig. 7.
(c)
in
:s
a) Comparator with offset compensation circuit b) preamplifier with
+- �
-+-
__
-
__
800
1200
Fs (MHz)
__
1600
2000
SFDR vs. sampling frequency
-25+--+t--+--t--+-t----1f---+--l
:s -50 +--+-f---.t...,.---+-:;-.t--h�---,t---t----cl
PMOS active load c) Sense amplifier based SR latch
05
Ql
iii
::. 00
�.0.5
.1.0.L.-
+-
__-
400
u.
VI
-75
100
Fig. II.
200
SFDR for
300
400
500
Frequency (MHz)
600
/in=
fs =
75 MHz and
700 800
1.54 GHz
oJ
_
o
Fig. 8.
--'--_----'.
10
20
REFERENCES
L-_--'-_----'-�____'
___'
__
30
code
40
50
60
[I] M. S. Sandhoon Hwang, et al. , "Design of a 1. 8 V 6-bit Folding
AID Converter with a 0.93[pJ/convstep] Figure­
IEICE Trans. Electron, pp. 213 -219, February 2008.
Interpolation CMOS
of-Merit", in
[2] S. Limotyrakis, et al. , "Analysis and simulation of distortion in folding
DNL of the circuit after offset calibration
AID converters", IEEE Trans. on Circuits and Systems
Analog and Digital Signal Processing, pp. 213 -219, March 2002.
and interpolating
II:
[3] K. Ohhata, et al. , "A 770-MHz, 70-mW, 8-bit subranging ADC using
for low input frequency is plotted in Fig. 10. The performance
results are compared with reported work in Table I.
VI.
Proc. of A-SSCC,
pp. 41
high-gain offset-canceling positive-feedback amplifier in 90nm digital
CMOS", in
CONCLUSION
A 6-bit low-power subranging ADC has been simulated to
obtain an increased throughput using a new analog pipeline
with 1/2 Tck delay. Low power has been achieved by using
minimum size devices and a digital offset calibration method
has been used to reduce the effect of comparator offset.
-
VII.
reference voltage precharging architecture", in
-44, November 2008.
[4] Y. Shimizu, et al. , "A 30mW 12b 40MS/s subranging ADC with a
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90nm CMOS", in
2007.
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[6] P. M. Figueiredo, et al.
step subranging ADC", in
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90-nm CMOS",
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pp. 2320 -2329,
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ACKNOW LEDGMENT
[8] Yuan-Ching Lien, et al. , "A 6-b I-GS/s 30-mW AOC in 90-nm CMOS
The authors acknowledge Government-of-India Special
Manpower Development Program (SMDP) for providing fi­
nancial support and Europractise for providing foundry­
specific designkits. The authors would also like to thank VLSI
Lab users of Indian Institute of Technology Bombay for the
fruitful discussions during VLSI meetings.
500
technology", in
[9] Y. Asada, et
Proc. of A-SSCC,
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