A Generic Analytical Model of Switching
Characteristics for Efficiency-Oriented Design and
Optimization of CMOS Integrated Buck Converters
Rohit Modak and Maryam Shojaei Baghini
VLSI Design Lab, Department of Electrical Engineering
Indian Institute of Technology(IIT)-Bombay, Mumbai 400 076, India
Email: {rohitmodak,mshojaei}@ee.iitb.ac.in
Abstract—Power management and supply generation is an
important issue in SOCs (System On Chips). Design of on-chip
CMOS buck converters for maximum efficiency needs models
which can predict different kinds of losses in the converters. In
this paper a generic analytical model for switching times and
accordingly I-V overlap losses for on-chip CMOS synchronous
buck converters is presented. The model features the derivation
of the delay on the basis of change in the stored charge during
switching of internal capacitances. Therefore the proposed model
needs only a few process parameters to estimate the delays and
accordingly I-V overlap losses. Another feature of the presented
model is that it’s independent of the switch driver and is
applicable to a wide range of input voltage and load conditions.
The proposed model is implemented in MATLAB and verified
against detailed CADENCE Spectre simulations for integrated
buck converter design and optimization. Estimations from the
model match detailed simulation results for the input voltage
range of 2.8 V to 5 V and load current range of 65 mA to 200
mA, which are also presented in this paper. We demonstrate
application of the proposed model for elaborative and efficient
design space exploration for efficiency-oriented design of buck
converters.
I. I NTRODUCTION
DC-DC converters are extensively used in mobile devices
like cellphones, PDAs and digital cameras. These converters
provide regulated DC voltage by converting the battery output
voltage to the required levels. As more and more devices
are being accommodated on a single chip and the operating
frequencies are increasing, it is imperative for the converters
to be highly efficient. Generally the converters used in mobile
and portable devices are low power output. The output current
does not exceed a few hundred milliamperes. Among DCDC converters, buck converters are very popular as these type
of converters exhibit high conversion efficiency and voltage
regulation [1]–[3] compared to others. Fig. 1 shows the basic
schematic of a typical buck converter. PWM (Pulse Width
Modulation) block alternately switches PMOS and NMOS
transistors, S1 and S2. As a result a periodic rectangular
waveform is generated, which is applied to the low pass
filter, composing inductor L and capacitor C. Duty cycle of
switching depends upon the output voltage. Buck converter
can either be implemented off-chip or can be integrated along
with the other modules of SoC (system on chip). Integrating
the switching devices and control circuitry on the same IC
Fig. 1.
Buck converter.
(integrated circuit) along with the rest of the modules of SoC
reduces the losses due to off-chip parasitics and interconnects.
Thus, efficiency of an integrated converter is more compared
to an off-chip converter [4].
A. Different Losses
There are three major sources of power loss in power buck
converters [5]. Similar losses exist in integrated CMOS buck
converters.
a) Conduction losses: These are due to the power dissipation in all components of the converter when they are
ON and conduct the current. For example losses due to ON
resistance of the transistors, diode forward voltage drop and
parasitic resistance of inductor and capacitor.
b) Switching losses: They constitute power dissipation
which occurs during switching of components. Switching
losses depend on the switching frequency. For example when
a transistor switches from OFF to ON (triode region) there is
a considerable power dissipation (IV ) during the transition.
This transient power dissipation is known as I-V overlap
loss. Commonly-known F CV 2 loss originating from charging
and discharging of capacitors (e.g gate capacitors) is another
example of switching losses.
c) Reverse recovery losses: It takes time for a diode
operating in forward-bias region to switch to reverse bias.
During this time diode will draw a reverse current to store
the required amount of charge. In the buck converter shown
in Fig. 1, the reverse current of the body diode of NMOS
transistor is drawn from the PMOS transistor while it’s turning
on. This leads to power dissipation in the PMOS switch as
well as energy consumption to charge the body diode. Reverse
recovery loss is in fact a part of switching loss. However to
distinguish it from other switching losses due to charge and
discharge of parasitic capacitances it is considered separately.
Efficiency (η) of a buck converter is given by
η=
Pout
,
Pout + Ploss
(1)
where Ploss is total average dissipated power and Pout is
power delivered to the load. Ploss is composed of
Ploss = Pcond + Psw + Prr + Pgate
+Pdriver + Pcontroller
(2)
In Eq. (2) Pcond is the conduction power loss, Psw is the
switching loss, Prr is the reverse recovery loss, Pgate is
the power dissipated because of charge/discharge of gate
capacitors, Pdriver and Pcontroller are the power dissipated
in driver and controller respectively. In this design Pdriver +
Pcontroller is 10 mW.
B. Design parameters
To maximize the efficiency of a CMOS buck converter,
circuit parameters should be optimized. One of the main
design parameters is the size of switches. As size of the switch
increases, conduction loss decreases whereas switching loss
increases. Switching frequency has a strong impact over the
converter efficiency and size of the passive components. The
converter switching frequency is increasing so that the size
of passive components can be reduced and stringent transient
requirements of future microprocessors can be met [6]. For low
power output buck converters operating at high frequencies,
switching losses are significant.
In order to prevent current shoot-through, in the synchronous buck architecture some dead time has to be ensured
between switching ON of one switch and switching OFF of
the other, particularly between turn-ON of pull-up switch and
turn-OFF of pull-down switch. Inductor current is supported
by the body diode of NMOS switch during dead time, which
in turn leads to conduction loss in the body diode. Therefore
knowledge of switching times is critical in deciding the dead
time.
To achieve the maximum efficiency, design parameters like
size of switches, dead time and switching frequency need
to be optimized through an iterative optimization procedure
over the entire range of input voltage and load current. This
procedure requires a transistor level simulator to be invoked
iteratively in the optimization loop to accurately quantify the
losses. For each simulation it takes several hundred cycles
for a buck converter to reach to its steady state. Apart from
this aspect, simulation step size of a few nanoseconds or even
less may be required for accurate analysis during switching
on/off transitions. Available commercial circuit simulators are
not fast enough for these long simulations as the transistor
models (e.g BSIM3 or BSIM4 [7]) are too complex. Therefore
an analytical model of various losses in a buck converter will
be of great importance for the designer to reduce the design
and optimization time. Analytical models for different losses in
a buck converter have been reported in many research works.
Fairly accurate model for conduction losses in the switches,
parasitic series resistance of the inductor, capacitor and the
body diode are reported [1], [8]. However, a comprehensive
and general model for I-V overlap loss during switching
transition is needed to accurately estimate the efficiency.
Contribution of I-V overalp loss during switching transitions
is significant in low power converters and they might even
dominate the losses at low load conditions.
Previous models of I-V overlap loss either rely on precharacterized discrete power MOSFETs as switches [9] and/or
assume current mode drivers [10], [11]. However the trend
is to implement the low power buck converters in standard
CMOS technologies. In [4], an unknown optimum value of
the width of the transistor switches is used to maximize the
efficiency. However no expression for the switching times and
different losses is given. In [6], the reported model is valid
only for the switches driven by specific resonant gate driver
and in [8] the proposed model is almost completely empirical.
Another aspect of reported models is that the reverse recovery
loss is excluded from the I-V overlap loss and is not verified
with circuit simulations. Thus, an analytical model relating
the technology parameters to the losses independent of driver
would be very useful for the designer. It should be noted that
I-V overlap loss occurs during the switching of both PMOS
as well as NMOS switch. However PMOS loss is dominant
as the voltage switched across NMOS is small.
C. Our contribution and organization of the paper
In this paper a generic analytical model for I-V overlap
loss during switching of PMOS switch of an integrated synchronous buck converter based on a few process parameters
in standard CMOS technologies is presented. The presented
model is independent of the driver and is applicable to a wide
range of input voltage and load conditions. The model predicts
the switching times and I-V overlap losses in the PMOS switch
and body diode, with an accuracy of ±10 %, with reduced
design time. The accuracy achieved is good enough for initial
design before detailed circuit optimization. The presented
model is implemented in MATLAB. The program run time
is much faster compared to the commercial circuit simulators. The model is verified using Cadence Spectre simulator.
Losses are calculated in CADENCE using CALCULATOR
tool. Application and effectiveness of the proposed model to
the design and optimization of a buck converter in 0.35 µm
CMOS process under different values of input voltage ranging
from 2.8 V to 5 V, load current ranging from 65 mA to 200
mA and output voltage of 1.8 V is also demonstrated.
The rest of the paper is organized as follows. In Section
II, we discuss the analytical model for switching loss and
switching time of PMOS transistor in synchronous buck
converters. In Section III, we compare the results from the
model and those from detailed circuit simulation. Application
of the model in optimization of design parameters is discussed
in Section IV. Concluding remarks are presented in Section V.
II. M ODELING OF
SWITCHING TIME AND
LOSSES
I-V OVERLAP
This section presents the analytical model for I-V losses and
switching times of the integrated PMOS switch in the buck
converter independent of the switch driving characteristics.
Notations- Through out this paper Fsw denotes the frequency of PWM output voltage. Vin and Vf refer to supply
voltage and forward bias voltage drop of the body diode of
NMOS transistor, respectively. Ip and Ib are the peak and
bottom values of the inductor current. ton and tof f are the
turn-on and turn-off times of PMOS switch. Io represents
load current. Qrr denotes the total change in the charge stored
in the body diode of NMOS transistor while switching from
forward bias to reverse bias.
Fig. 3. Linear approximation of current and voltage waveforms during PMOS
turn-on and turn-off.
A. Switching loss
Turn-on: Fig. 2 shows typical drain-source voltage and
drain current waveforms of PMOS transistor during switch-on
transition. The waveforms are real simulated waveforms for an
integrated buck converter in 0.35 µm CMOS technology. The
current rises above the inductor current because of the reverse
recovery phenomenon in the body diode of the NMOS switch.
It can be seen that drain voltage remains almost constant
during the time till drain current of PMOS transistor is less
than the bottom value of inductor current. This commonlyknown effect is attributed to the effect of total effective
capacitance existing at the drain terminal of PMOS transistor.
The current and voltage waveforms can be approximated with
linear waveforms as shown in Fig. 3.
The area of I-V overlap region can be evaluated in two
parts, I-V overlap when Id is less than Ib and that when Id
is more than Ib . The later one is due to reverse recovery. The
area under Id values more than Ib gives the reverse recovery
charge. Power dissipation due to the current overshoot is called
reverse recovery loss. Accordingly corresponding losses are
simply derived as follows:
Fig. 4. Current and voltage waveforms of body diode during diode turn-off.
PI−VON = Fsw
Z
ton
Vsd Id dt
(3)
0
(Vin + Vf )Ib Fsw ton
.
(4)
2
Power dissipation in PMOS transistor due to reverse recovery of the NMOS body diode can be written as
PI−VON =
Qrr Fsw (Vin + Vf )
.
(5)
2
Thus, the total I-V overlap loss during PMOS turn-on is
PrrP M OS =
Pon = PI−VON + PrrP M OS .
(6)
From the linear approximation shown in Fig. 4 power
dissipation in the body diode due to reverse recovery can be
estimated to be
Prrbd =
(7)
T1 − T0
. Parameter ‘a’ depends on the nature of
T2 − T1
reverse recovery of the diode (soft or snap recovery). For the
technology used, a = 1/3. This value of a was obtained easily
by running one simulation for characterizing the body diode.
Turn-off: Fig. 5 shows the simulated waveforms for drain
and gate current and drain-source and gate voltage during
where, a =
Fig. 2. Typical current and voltage waveforms during PMOS turn-on. Id
peaks to a high value due to reverse recovery in body diode of NMOS
transistor.
Qrr Fsw ( V3in + aVf )
,
1+a
source, the gate current waveform is a rectangle. The net
charge transferred to the gate of a switch can be written as
gpeak tof f
∆Q =
(I
2
Ig tof f ,
,
for tapered buffer driver
constant current driver
(12)
where Igpeak is the peak gate current shown in Fig. 3. Igpeak
is the driver specification. Cg is the total gate capacitance. For
our case of tapered buffer driver,
ton =
2Cg Vin
.
Igpeak
(13)
C. Turn-off time
Fig. 5. Current and voltage waveform during PMOS turn-off. Id drops
sharply at the end as body diode of NMOS starts conducting.
PMOS turn-off. These waveforms can be approximated to
linear waveforms shown in Fig. 3. Turn-off losses are derived
in a manner similar to loss derivation for PMOS turn-on.
During PMOS turn-off, from Fig. 3 Id and Vsd can be written
as
(Ip − Ix )t
Id = Ip +
(8)
tof f
Vsd =
PI−VOF F =
(Vin + Vf )t
tof f
(9)
(Vin + Vf )(Ip + 2Ix )tof f Fsw
6
(10)
2∆Q
,
tof f
(11)
Ix = Ip −
where ∆Q is the amount of change in the charge stored in
the drain junction capacitance (Cdb ) of PMOS transistor. ∆Q
is calculated from the time PMOS transistor starts switching
till onset of body diode conduction.
Considering the model demonstrated in Fig. 3, only a few
parameters need to be extracted for a given CMOS technology.
Qrr and Vf are transistor characteristics which can be easily
obtained by transistor level simulations. For example for 0.35
µm CMOS process values of Qrr and Vf are obtained to be 88
pC and 0.61 V, respectively. Ip is (Io +∆i) and Ib is (Io −∆i)
where ∆i is the inductor current ripple which is one of the
design specifications. For the calculation of switching losses
as stated earlier we need to know the switching times. The
model for ton and tof f proposed in this paper is based on
principle of charge transfer.
B. Turn-on time
In this section we estimate the turn-on time of the switches
based on generic charge transfer approach. For a switch driven
by series of standard tapered inverters, the gate current (Fig. 2
and Fig. 5) can be approximated by a triangular waveform as
shown in Fig. 3. For a switch driven by a constant current
During turn off, the channel stops as the gate voltage rises
above Vin + Vtp . However, it takes time for the large Cdb to
charge to Vin + Vtp . This is shown in Fig. 3, where drain
current of PMOS is nonzero even when the gate voltage
has charged to Vin . Therefore turn-off time, tof f is mainly
dependent on Cdb rather than Cg . By applying principle of
charge transfer, the net charge transferred can be expressed
as:
1
(14)
Qof f − Qon = Ip tof f
2
Qon = Cdbon Ip Ron
(15)
Qof f = Cdbof f (Vin + Vf )
(16)
tof f = 2(
Qof f − Qon
).
Ip
(17)
In Eq. (15) Ron is the channel resistance of PMOS switch.
Values of Cdb used to calculate the net transferred charge are
evaluated at two extreme points namely when PMOS is ON
(Vsd = Id Ron ) and when PMOS is off (Vsd = Vin + Vtp ).
III. V ERIFICATION
OF THE MODEL
To verify the proposed model at different conditions, a
CMOS buck converter was designed in 0.35 µm Mixed-Mode
TSMC process as reference. The converter was then simulated
using CADENCE Spectre simulator for different values of
input voltage and load. The proposed model was implemented
in MATLAB. The transistor switches and the tapered buffers
used as driver were implemented using I/O devices available in
0.35 µm Mixed Mode TSMC process. Aspect ratio for PMOS
was 45000 and that for NMOS was 22500. The specifications
of the designed buck converter are shown in Table. I.
The model proposed is verified over the entire load current
and input voltage range specified in Table. I. To demonstrate
validity of the model, figures 2, 5, 6, 7, 8 and 9 illustrate
Spectre simulation results at different values of input voltage
and load current. As shown in the figures turn-on and turnoff times from Eq. (13) and Eq. (17) match the corresponding
values from Spectre simulations. Comparison of modeled and
simulated switching times and I-V overlap losses is presented
in tables II and III. Table IV compares the modeled and
TABLE I
S YNCHRONOUS B UCK C ONVERTER S PECIFICATIONS
Technology
Switching frequency(Fsw )
Vin
Output Voltage(Vo )
Output current(Io )
Filter Inductance
Filter Capacitance
0.35 micron CMOS
1 MHz
2.8 V-5 V
1.8 V
65 mA-200 mA
10 µH
22 µF
Fig. 7. Simulated waveforms during PMOS turn-off at Vin = 3.3 V and Io
= 100 mA. tof f from simulation : 1.3 ns and that from model : 1.32 ns.
Fig. 6. Simulated waveforms during PMOS turn-on at Vin = 3.3 V and Io
= 100 mA. ton from simulation : 0.5 ns and that from model : 0.51 ns.
simulated losses in the body diode due to reverse recovery.
The proposed model is able to predict both the switching times
and losses with an accuracy of ±10 %.
IV. A PPLICATION OF
THE MODEL FOR OPTIMIZATION
As the model provides fairly accurate estimates of losses
and switching times, it can be utilized to derive and optimize
the parameters like transistor widths, dead time and frequency
over the defined input voltage and load current range. The
MATLAB implementation of the model was used to study
the variation in efficiency with switch sizes. Fig. 10 shows
the variation of efficiency with switch sizing at Io of 65mA.
It is clear from the result that at a particular load and line
condition, there exists a region of values of WP and WN
where efficiency peaks and remains same for slight variations.
Thus, designer can optimize the widths depending upon the
extent of variations of optimum widths with load and line
conditions. The optimum width decreases as input voltage
increases. Also, since we are able to reliably predict the
switching times at different load and line conditions, the dead
time can be adjusted. For the designed converter, across the
TABLE IV
L OSSES IN B ODY DIODE DUE TO REVERSE RECOVERY AT Io =100
MILLIAMPERES
Vin →
Io (mA)↓
65
100
Spectre
0.077
0.077
3.3 V
Model (Eq. (7))
0.084
0.084
Spectre
.121
0.122
5V
Model (Eq. (7))
0.123
0.123
Fig. 8. Simulated waveforms during PMOS turn-on at Vin = 5 V and Io =
100 mA. ton from simulation : 0.4 ns and that from model : 0.39 ns.
entire range of input voltage and load current, maximum value
of the switching time which happens during turn-off is 2 ns.
V. C ONCLUSION
An analytical model for switching times and I-V overlap
loss of PMOS transistor of an integrated synchronous CMOS
buck converter is presented in this paper. Reverse recovery
losses due to body diode of NMOS are quantified. The model
is verified using CADENCE Spectre simulations. I/O devices
in 0.35 µm Mixed Mode TSMC process are used for the
design of buck converter. Chain of tapered buffers is used
for the driver. The proposed model is able to predict both
the switching times and losses with an accuracy of ±10 %,
permitting the design space exploration for efficiency-oriented
design of buck converters. The effect of switch sizes on
efficiency of buck converter is explored with the proposed
model. Optimum switch size for maximum efficiency is shown
to decrease with increase in input voltage. Design also permits
optimization of dead time to maximize the efficiency.
TABLE II
S WITCHING TIME AND LOSSES AT Io =100 MILLIAMPERES
Vin
2.8 V
3.3 V
5V
ton (ns)
Model (Eq. (13))
0.72
0.51
0.39
Spectre
0.7
0.5
0.4
Spectre
1.2
1.3
1.5
tof f (ns)
Model (Eq. (17))
1.28
1.32
1.45
Spectre
0.23
0.24
0.3
Ponp (mW)
Model (Eq. (6))
0.24
0.26
0.28
Poffp (mW)
vline
Spectre
Model (Eq. (10))
.18
173
.21
0.212
0.38
0.38
TABLE III
S WITCHING TIME AND LOSSES AT Vin =5 V
Io (mA)
65
100
200
Spectre
0.4
0.4
0.4
ton (ns)
Model (Eq. (13))
0.39
0.39
0.39
Spectre
2
1.5
0.8
tof f (ns)
Model (Eq. (17))
1.97
1.45
0.88
Spectre
0.28
0.3
0.37
Ponp (mW)
Model (Eq. (6))
0.27
0.28
0.4
Fig. 11.
Spectre
0.34
0.35
0.38
Poffp (mW)
Model (Eq. (10))
0.35
0.36
0.38
Effect of load and line conditions on efficiency.
Fig. 9. Simulated waveforms during PMOS turn-off at Vin = 5 V and Io =
100 mA. tof f from simulation : 1.5 ns and that from model : 1.45 ns.
Fig. 10. Effect of switch sizes on efficiency. WP and WN denote the width
(in mm) of PMOS and NMOS respectively.
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