OPEN SYSTEM-ON-CHIP PLATFORM
FOR EDUCATION
Don Bouldin, Ph.D.
Rishi Srivastava
Electrical & Computer Engineering
University of Tennessee
Knoxville, TN 37996-2100
dbouldin@tennessee.edu
A
D
C
R
A
M
CPU
FPGA
DCT
ENCRYPTION
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QUESTIONS ADDRESSED
BY THIS PRESENTATION
• How do we teach students to create and reuse
components?
• What is the role of a programmable SoC platform?
• Why design a mask-based SoC platform?
• Why do we want the SoC platform to be open?
• Where can we find high-quality cores for free?
• How do we assemble these cores?
• What can we do with this open SoC platform?
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MOTIVATION
• Million-gate ICs are increasingly being designed as system-on-chip
(SoC) platforms.
• Students need to learn how to reuse existing components and how
to create new ones.
• A SoC platform provides:
– opportunity to create and merge new components
– support for team design
– significant net-list for optimization at the synthesis level
– significant net-list for optimization at the physical level
• An open SoC platform also provides:
– visibility that facilitates learning
– availability to all for free
– opportunity for collaborations
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PROGRAMMABLE SOC PLATFORMS ARE USEFUL
• A programmable SoC contains a hard (or soft) CPU.
• Thus, these programmable platforms support:
– Team Design of/with virtual components
– HW/SW Co-Design
– Real-time embedded systems
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MASK-BASED SOC PLATFORMS PERFORM BETTER BUT
HAVE ADDITIONAL REQUIREMENTS
• Mask-based ICs are faster and less power-consuming than FPGAs.
• However, mask charges are $1.6M for 90-nm CMOS so the number of
design starts is declining.
• Furthermore, mask-based implementations require designers to
include provisions for testing manufacturing faults.
• Also, designers must perform more simulation to avoid re-spin charges
due to physical issues (crosstalk, clock skew, noise, etc.).
• Mask-based SoC platforms are becoming common to reduce risk.
0.9
0.9
0.9
0.9
0.9
0.9
Interconnect 0.9 so
0.9x0.9x0.9x0.9x0.9x0.9x0.9 = 0.5
1.0
1.0
1.0
1.0
1.0
0.9
Interconnect 0.9 so
1.0x1.0x1.0x1.0x1.0x0.9x0.9 = 0.8
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OUR OPEN SOC PLATFORM ALLOWS NEW COMPONENTS
TO BE ADDED TO A CPU VIA ON-CHIP BUSES
New
New Components
Components
CPU
CPU
with
with
On-chip
On-chip
buses
buses
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LEON CPU CAN BE DOWNLOADED
FOR FREE AND INCLUDES CROSS-COMPILER
• .
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COMPONENTS CAN BE DOWNLOADED
FOR FREE FROM OPENCORES.ORG
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ADDITIONAL OPEN COMPONENTS CAN BE
DOWNLOADED OR DEVELOPED LOCALLY
•
•
•
•
•
•
•
Analog
Digital Cores
Digital Peripherals
MEMS
Bondpads and ESD
Design Methodology
Design Tools and Scripts
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OUR DESIGN AND VERIFICATION FLOW
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DESIGN SPACE EXPLORATION
AT THE SYNTHESIS LEVEL
Synopsys
Power
Compiler
can
produce
multiple
powerdelayarea
solutions
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TEST GENERATION FOR ASIC
MANUFACTURING FAULTS
Combinational Test Pattern Generation starts:
Start random pattern generation:
…
Num.
Num. Faults
Faults detected:
detected: 2648
2648
98.10% faults processed ;
Num.
cumulative fault coverage = 98.10%
Num. Test
Test Patterns:
Patterns: 161
161
Start deterministic pattern generation
...
100.00% faults processed ;
cumulative fault coverage = 99.85%
Test
Test Generation
Generation Time:
Time:
(CPU)
(CPU) 0.94
0.94 sec
sec
Synopsys
Synopsys Test
Test Compiler
Compiler
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DESIGN SPACE EXPLORATION
AT THE PHYSICAL LEVEL
Floorplanning produces different layouts
Cadence First Encounter
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SIGNAL AND POWER INTEGRITY ISSUES
CAN BE STUDIED
.
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SUMMARY AND CONCLUSIONS
• A SoC platform permits students to create and
reuse components.
• Students can practice using a programmable
SoC platform.
• A mask-based SoC platform requires students
to learn about testing and physical issues.
• An open SoC platform facilitates learning,
design space exploration and collaboration.
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