NOMENCLATURE
Design and Development
of a Real-Time DSP and
FPGA-Based Integrated
GPS-INS System for Compact
and Low Power Applications
V. AGARWAL, Senior Member, IEEE
H. ARYA
S. BHAKTAVATSALA
Indian Institute of Technology–Bombay
Emphasis of the present work is on an elegant real-time
solution for GPS/INS integration. Micro-electro mechanical
system (MEMS) based inertial sensors are light but not accurate
enough for inertial navigation system (INS) applications. An
integrated INS/GPS system provides better accuracy compared
with either INS or GPS, used individually. This paper describes
an improved design and fabrication of a loosely coupled INS-GPS
integrated system. The systems currently available use commercial
off-the-shelf (COTS) hardware and are, therefore, not optimized
for compact, single supply, and low power requirements. In the
proposed system, a digital signal processor (DSP) is used for
inertial navigation solution and Kalman filter computations.
A field programmable gate array (FPGA) is used for creating
an efficient interface of the GPS with the DSP. Direct serial
interface of the GPS involve tedious processing overhead on
the navigation processor. Therefore, a universal asynchronous
receiver transmitter (UART) and dual port random axis memory
(DPRAM) are created on the FPGA itself. This also reduces the
total chip count, resulting in a compact system. The system is
designed to give real time processed navigation solutions with an
update rate of 100 Hz. All the details of this work are presented.
Manuscript received December 2, 2005; revised January 9 and
December 28, 2007; released for publication March 29, 2008.
IEEE Log No. T-AES/45/2/932997.
Refereeing of this contribution was handled by Tahk.
Authors’ current addresses: V. Agarwal, Dept. of Electrical
Engineering, Indian Institute of Technology–Bombay,
Powai, Mumbai, Maharashtra 400 076, India, E-mail:
(agarwal@ee.iitb.ac.in); H. Arya, Dept. of Aerospace Engineering,
Indian Institute of Technology–Bombay, Powai, Mumbai,
Maharashtra 400 076, India; S. Bhaktavatsala, KLA-Tencor
Software India Pvt. Ltd., Chennai, India.
c 2009 IEEE
0018-9251/09/$25.00 °
ADC
ANSI
COTS
DOS
DPRAM
DSP
EKF
EOC
FDC
FPGA
GIDAC
GPS
IMU
INS
INT0
INT1
ISR
JTAG
MAV
MCDMA
MEMS
MFLOPS
NCU
NMEA
NPC
PAL
RISC
SINS
SRAM
TTL
UART
VHDL
VLSI
SDLC
Analog-to-digital converter
American National Standards Institute
Commercial off-the-shelf
Disk operating system
Dual port random axis memory
Digital signal processor
Extended Kalman filter
End of conversion
Flight dynamic control
Field programmable gate array
GPS and IMU data acquisition card
Global positioning system
Inertial measurement unit
Inertial navigation system
Interrupt 0
Interrupt 1
Interrupt service routine
Joint test action group
Mini aerial vehicle
Micro-programming controlled direct
memory access
Micro-electro mechanical system
Million floating pointing operations per
second
Navigation computer unit
National Marine Electronics Association
Navigation processor card
Programmable array logic
Reduced instruction set computer
Strapdown inertial navigation system
Static random access memory
Transistor transistor logic
Universal asynchronous receiver
transmitter
VLSI hardware description language
Very large scale integration
Synchronous data link control.
I. INTRODUCTION
For accurate functioning of autonomous navigation
systems, reliable position information in real-time
must be available at regular intervals of time. High
accuracy inertial measurement units (IMUs), used
in avionic systems, exhibit superior performance
specifications. However, the high cost and weight
of a standard inertial navigation system (INS) limits
its application in general areas, such as navigation
and positioning of mini aerial vehicles (MAV) [1].
With the development of low cost micro-electro
mechanical systems (MEMS) devices, however, the
situation has changed. Commercial off-the-shelf
(COTS), MEMS-based IMU systems have proved
to be highly popular and feasible for autonomous
navigation systems [1—9]. These systems are cost
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2
APRIL 2009
443
effective, compact and light weight. But they have an
inherent limitation–that of precision.
This limitation is overcome by the use of extended
Kalman filter (EKF), augmented by GPS estimates
[1—9], leading to the integration of INS and GPS. The
time critical nature of autonomous navigation systems
requires that processing of INS computations and EKF
algorithm should be completed before the next update
from the IMU sensors. This imposes severe constraint
on the integration software, processor speed, and
system’s architecture. Only a few papers are available
[3—6] that are related to the hardware development of
such systems.
Many of the available integrated INS/GPS systems
either have used a serial interface link or multiplexed
analog-to-digital converter (ADC) for INS data
acquisition [1—9]. Serial interface of sensor output
involves a tedious processing overhead on navigation
processor. Further, with the multiplexed-type ADC,
all the position information being considered
for calculations may not correspond to the same
instant [2—9]. Accurate estimates of position and
attitude can be obtained using integration technique.
Different techniques of GPS-INS integration have
been implemented to predict accurate position
information in navigation systems. A loosely coupled
integrated approach [1, 4] using a GPS receiver and
a low cost strap down INS, is used to overcome
the sensor errors or random disturbances. Different
errors that are present in an accelerometer and a
gyroscope are bias, scale factor, drift, and input/output
nonlinearity. Most of the systems discussed [3—5, 7]
are based on the commercially available embedded
computer boards and COTS hardware. This hardware
may not be optimized for the space and power
constraints imposed by a given application as they
are general purpose hardware. This may cause space
and reliability problems which are very critical for
aerospace applications. The existing systems also
require power supplies at different levels, causing
space, weight, and volume constraints. Also, all the
integrated systems discussed employ either two or
more power supplies [3, 4] for their operation.
Many papers have reported the processing of the
GPS and IMU signals offline [7], i.e., IMU signal and
GPS data are collected in real time and its processing
for INS solution and the Kalman filter integration
is done off line. The correctness of the real-time
integrated GPS-INS systems depends not only on
the logical result of computation, but also on the time
duration during which the results are produced. When
the system has more computation intensive tasks to
perform, dedicated DSPs are used as the processor.
The inertial navigation computation is performed at
100 Hz. This inertial data is then integrated with the
GPS data (position, velocity, course) at 1 Hz. This
is a simple strategy and requires continuous valid
GPS measurements. IMU data is also coupled with
444
Fig. 1. Loosely coupled integrated GPS-INS system.
Fig. 2. Tightly coupled integrated GPS-INS system.
raw measurement (pseudo range and carrier phase)
of GPS, as it is more robust and can work with less
number of GPS measurements [10].
Coupling of low cost inertial sensors with GPS is
broadly classified as follows.
1) Loosely coupled system.
2) Tightly coupled system.
3) Ultra-tightly coupled system.
a) Loosely coupled system: In this system GPS
data, i.e., position, velocity, etc. are coupled with INS
data using an EKF as shown in Fig. 1. It is highly
dependent on the availability of GPS data. In the
present work, a nine state Kalman filter is used.
b) Tightly coupled system: In this system the
INS data is directly fused with GPS raw measurement
data inside the GPS Kalman filter. It is more robust
compared with the loosely coupled system. However,
it is also more complex. There is no separate GPS
Kalman filter used in GPS position calculation. The
GPS update is used to calibrate INS, while the INS
is used to aid the GPS receiver during interference.
The external navigation filter receives raw GPS
measurement of pseudo-range and Doppler or delta
range. The raw GPS observations are directly passed
on to the combined GPS/INS Kalman filter as shown
in Fig. 2. The main advantage here is that the solution
can use the GPS measurement update even if there are
less than four satellites available. But errors might be
induced due to the reduced observability of the states.
c) Ultra-tightly coupled system: An INS can
aid a GPS receiver at different levels. INS output
of position, velocity, and attitude, used as external
input to the GPS receiver, aid in prepositioning
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2 APRIL 2009
Fig. 3. Architecture of integrated GPS-INS system proposed by
Shang et al. [3].
calculation for faster signal acquisition and in
interference rejection during signal tracking. This type
of integration method requires access to the receiver’s
firmware. As a result, this scheme of integration
is usually implemented only by the equipment
manufacturer.
Apart from Kalman filter and EKF, several other
filters have also been used for integrated INS-GPS
solutions. For example, the particle filter [11] has
been used in place of the EKF. Rao-Blackwellized
filters [11] have been used to reduce the variance
of the state estimates. Some authors have reported
the use of artificial neural network based techniques
[12] to track the direction changes and mimic the
motion dynamics utilizing the latest available INS
and GPS data. The use of Bayes filter [13] has also
been reported for GPS-INS integration. Improvement
in GPS and GPS-INS integrated navigation systems
has been proposed by incorporating more robust
techniques in fusing the data [14, 15].
Multiple GPS can be used for attitude
determination using carrier phase information. But
such a system will be bulky and will require a
reasonable separation distance between the two GPS
antennas for good accuracy. Such systems are reported
in literature for aiding INS where space and weight
are not major concerns [16]. In the presented work a
single, 12 channel GPS receiver (Laipac TF11 make)
with SIRF II as core, is used which works with 5V
power supply [17]. Various INS/GPS configurations
found in the available literature are summarized below.
An integrated system, based on PC/104 embedded
microcomputer operating on three different power
supplies is described by Shang et al. [3]. The system
architecture, as shown in Fig. 3, uses a PC/104
bus for data transfer from ADC to an embedded
computer. In this work, multiplexer-based A/D
conversion of inertial sensor signals is achieved using
customized data acquisition board. Real-time data
calculation and rapid data exchanging is achieved
using micro-programming controlled direct memory
access (MCDMA) technique.
An integrated system based on low cost IMU
and GPS receiver has been proposed by Moon et al.
[4]. In this work, an IMU sensor with a navigation
computer unit (NCU) is interfaced using serial
communication. The NCU operates in a multi-tasking
environment using pSOS+ real-time operating system.
In another architecture, analog sensor signals are
Fig. 4. Architecture of integrated GPS-INS system proposed by
Lichuan et al. [9].
interfaced with the NCU using serial data link [9].
NCU is based on a high speed reduced instruction
set computer (RISC) floating point processor and is
operated in multi-tasking environment (Fig. 4).
Faulkner et al., [5] have described a development
program in which a PC/104 computer is used for
loosely coupled system and digital signal procesor
(DSP) based navigation processor is used for
developing the closely (tightly) coupled integrated
system. Serial link communication is operated at
higher baud rates and a modular integrated navigation
Kalman filter has been used in their prototype system.
The system developed by Hegg [6] uses six
different power supplies for their integrated scheme.
Data from IMU sensors is transferred through serial
communication to the navigation processor. Some
attractive features of their system are: in-space
initialisation, flight control output signals, and other
redundancy management platforms are provided.
Bridging GPS outages for tens of seconds using a
low cost inertial device, and integration with GPS
information and its feasibility are described by Cao
et al., [7, 8]. Results show that the position accuracy
of a low cost strapdown INS (SINS)/GPS is just
the same as that of the GPS receiver when the GPS
data is available. A position error of 10 m after 10 s
with complete loss of GPS signals is observed in this
system.
This paper proposes a new architecture for an
elegant integrated GPS-INS system with improved
data acquisition, processing overheads, interfacing
technique, and time criticality issues. Details of the
development of a real-time system based on floating
point DSP suitable for autonomous navigation systems
are presented. It may be noted that the emphasis is
on real time issues related to hardware integration. A
loosely coupled integrated approach [1, 4] is chosen
to overcome the sensor errors and obtain accurate
estimates of position and attitude. The whole system
uses a single power supply of 9V. Though various
circuits and ICs work at different voltage levels, the
PCBs are designed in such a way (using voltage level
shifter circuits), so that a single 9V source is able
to feed all the circuit boards. Further, the proposed
system is more compact and reliable due to the use of
configurable field programmable gate array (FPGA)
for GPS data acquisition and DSP interface.
AGARWAL ET AL.: DESIGN AND DEVELOPMENT OF A REAL-TIME DSP AND FPGA-BASED
445
Fig. 5. Proposed system architecture.
To summarize, the scheme proposed in this paper
offers the following advantages:
1) processing GPS data on a reconfigurable FPGA
chip which ensures compactness and reduced weight;
2) DPRAM on an FPGA for asynchronous GPS
data transmission between GPS and DSP;
3) use of a single power supply which reduces
size, weight, and volume;
4) use of specially designed, dedicated hardware
that is optimized for speed, size, and power.
The remaining part of this paper is organized as
follows. System architecture of the proposed system
is described in Section II. In Section III, real-time
implementation details of both the hardware and the
software are presented. Results and discussions are
included in Section IV, followed by conclusions of
this work in Section V.
II. PROPOSED SYSTEM ARCHITECTURE
The proposed integrated system with a lightweight
package providing the navigation system function
is shown in Fig. 5. For better understanding, the
system can be divided into two main blocks and their
subblocks as below:
A) GPS and IMU data acquisition card (GIDAC)
1) analog signal acquisition
2) GPS serial data acquisition.
B) Navigation Processor Card (NPC).
The proposed architecture is now explained in details.
A. GPS and IMU Data Acquisition Card
GIDAC consists of two parts. The first part is
the analog signal acquisition block which processes
IMU signal input and converts them into digital data.
The second part handles the GPS data. FPGA-based
processing of the GPS signal is carried out to extract
data from the required “fields” of the GPS data train.
This data is sent to the NPC.
1) Analog Signal Acquisition: The analog
signals from IMU are passed through a second-order
Butterworth low-pass filter, and scaled to data
acquisition input range and sampled simultaneously,
thus preserving the phase information among all the
446
Fig. 6. Sampling of input signals. (a) Sampling of input signals
using multiplexer at input stage of ADC. (b) All input signals are
sampled at the same instant of time.
signals in the GIDAC card. As seen in Fig. 6, there
is a delay (¢) between the sampling of each input
signal in case a multiplexer is used at the input stage
of ADC. Thus, there is a delay of 5¢ by the time
the sixth input signal is sampled. Considering ax,
ay, az, p, q, and r as input channels ch1 to ch6, the
position information being considered for calculation
from all input signals is not actually correct as it
does not belong to the same time instant due to
the delays [3—6]. It may be noted that even if all
channels are not sampled simultaneously, but the
sampling and A/D conversion rate are significantly
high, then the effect of errors due to phase delays
will be minimal. Nonsimultaneous sampling will have
impact if computation cycle time is comparable with
conversion time. In the present case simultaneous
sampling helps in saving valuable DSP time which
is otherwise used for controlling the ADC, whereas
the correct relative information among all the signals
(ch1 to ch6) is maintained by simultaneous sampling.
2) PS Serial Data Acquisition: To relieve the main
processor from processing overheads during slow
speed serial I/O operation, FPGA-based serial port
interface is used in the proposed architecture. The
FPGA chip is programmed to receive the GPS data
from GPS receiver, and generates a busy signal when
accessing the in-built dual port RAM (DPRAM). This
low-going busy signal interrupts the DSP processor,
and the processor fetches the data from the internal
DPRAM of the FPGA chip.
B. Navigation Processor Card
The INS computations and integration with GPS
data are carried out on a floating point TMS320vc33
DSP present on the NPC card. Control logic signals
for selecting peripheral chips are generated using
the programmable array logic (PAL). Asynchronous
communication is maintained between the GPS
module and the NPC card using DPRAM, thus saving
the processor time during data transfer.
The design implementation of the prototype
integrated GPS/INS sytem, software flow of the
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2 APRIL 2009
Fig. 7. INS data acquisition board developed.
entire system, INS computations, and Kalman filter
implementation are discussed in detail in the next
section.
III. HARDWARE AND SOFTWARE IMPLEMENTATION
This section describes the hardware and software
implementation of the proposed scheme which is
operated on a single +5 V supply.
A. GPS-INS Data Acquisition Card (GIDAC)
As described in Section II, this card has two
stages:
1) INS data acquisition
2) GPS data acquisition.
1) INS Data Acquisition: Low cost dual axis §2 g
accelerometer ADXL202E [18] and §300± /s gyro
ADXRS300 [19] from analog devices are selected as
inertial sensors. These two sensors are operated on
a single supply +5 V, and give 2.5 V as their initial
null value in both the sensors. The sensitivity of the
accelerometer and gyro is 312 mV/g and 5 mV/± /s,
respectively.
Analog sensor output signals are filtered using
second-order Butterworth filter and preprocessing
of the sensor signal is performed before data
acquisition to make it compatible with the data
acquisition input requirements. Single-supply
operated, OP491 quad op-amp [20], with features
such as rail-to-rail inputs and outputs, is used to
build the multi-stage filters and to maintain high
signal-to-noise (S/N) ratios. A 16 bit, 250 kHz ADC
from Texas Instruments (ADS8364) [21] is chosen
for sampling all the channels simultaneously. The
developed printed circuit board for the INS data
acquisition circuit is shown in Fig. 7. The input
channels are grouped into pairs for high-speed
simultaneous signal acquisition, and offer high-speed
parallel interface in cycle mode (Fig. 8). The
control signals are generated from the NPC card
for accessing the signals. The time sequence of the
control signals of the ADC is shown in Fig. 8. The
various control signals/lines, of the ADC used, are as
follows:
1) start of conversion for all the six channels,
2) end of conversion for all the channels (two at a
time),
3) chip select to enable read from ADC (six low
going pulses),
4) read signals to ADC (six low going pulses).
As shown in Fig. 8, making the /HOLDx pin low,
places all the sample-hold amplifiers in the hold state
simultaneously and the conversion process is started
on each channel. The output data for each channel is
available as a 16 bit word from channel A0 through
channel C1.
Fig. 8. Experimental waveforms of ADS8364 showing simultaneous sampling.
AGARWAL ET AL.: DESIGN AND DEVELOPMENT OF A REAL-TIME DSP AND FPGA-BASED
447
Fig. 10. NPC board layout.
Fig. 9. GPS receiver serial link interface implemented on FPGA
for proposed system.
2) GPS Data Acquisition: GPS transmits data
using RS232 protocol. This data is further sorted out
to extract the useful information. Conventionally, a
microcontroller and a DPRAM are used to perform
this job. However, in this approach, both hardware
components remain underutilized. Alternately, an
FPGA-based system will render a single chip solution
with a small board size and can operate on a single
power supply. The development is not very trivial
compared with a microcontroller-based system. In
the presented study, an FPGA-based solution is
implemented as explained below.
The National Marine Electronics Association
(NMEA) sentences [17], received from the GPS
receiver, are fed into the FPGA chip. This FPGA
chip is operated at 8 MHz and programmed using
the very large scale integration (VLSI) hardware
description language (VHDL) code [22]. A clock
divider circuit (to generate the desired baud rate), a
receiver (RDR receiver), a RAM, and a DPRAM are
all realized on the FPGA chip itself. This is shown in
Fig. 9.
The receiver is based on the state machine of a
universal asynchronous receiver transmitter (UART)
of a microcontroller. The RDR receiver (Fig. 9)
computes the check sum of the received data and
crosschecks with the received GPS sentence data.
These data are temporarily stored in the RAM within
the FPGA chip, and once the checksum matches, the
RDR receiver generates update flag, enabling the
transfer of GPS data to the internal DPRAM of the
FPGA along with a low (busy) DPRAM signal, which
is sent as an interrupt to the navigation processor.
B. Navigation Processor Card
This card is built around a DSP TMS320vc33 chip
[23, 24] and other control electronics. It is a floating
point processor and provides up to 150 million
floating point operations per second (MFLOPS). It has
448
a 34K word dual access static random access memory
(SRAM), boot loader, and on-chip peripherals. Its
power requirements are minimal. The DSP chip is
operated with 1.8V and 3.3V, whereas the external
interface to this card is based on transistor transistor
logic (TTL). A 74LS4245 level shifter with buffer
is provided at the input and output stage of the
NPC card. Control logic signals are generated using
programmable array logic PAL22V10 chip. The NPC
board layout is shown in Fig. 10.
The NPC board can communicate with the host
PC either through parallel port or JTAG cable. The
applications are developed on host PC. The program
code is downloaded and run in DOS emulator mode.
This card gets digitized sensor inputs from the GIDAC
card. Inertial navigation computing is performed at
100 Hz, and the inertial data is fused with the GPS
data at 1 Hz (Fig. 11). Inertial/GPS sensor fusion
amounts to dynamically determining weights which
are combined with the position determined by the
INS data and the position output from the GPS
receiver.
The software flow of GPS-INS integration code
has several subprograms and header files, along with
assembly coding for initialisation of DSP [25] and
its peripherals. Timer0 and Timer1 are configured
using Timer Global control registers and Timer
Period registers in the initialisation routine. In the
interrupt vector table, /INT1 and /INT0 are defined
as interrupts from IMU and GPS data acquisition
process. Interrupt /INT0, received from the FPGA
chip (GPS update every 1 s), is considered a highest
priority. A variable “count = 2” is initialized for
counting EOC (/INT1) signal from ADC. Variables
Start INS and GPS available are set low. Timer0 is
dedicated for generating a clock of 5 MHz (for ADC)
and Timer1 for generating interrupts at a frequency of
100 Hz. These timers are enabled by configuring the
Timer Count register.
ADC chip is initialized by giving software
reset and configured to operate in CYCLE MODE.
Whenever Timer1 overflows (i.e., the overflow flag
gets set), the /HOLDx signals are made low, thus
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2 APRIL 2009
Fig. 11. (a) Flowchart showing different ISR tasks. (b) Flowchart showing software flow of proposed system.
making the ADC to sample all the six channels
simultaneously. So, the main program waits in
an infinite loop (IDLE mode) and based on the
interrupts, the respective interrupt service routines
(ISRs) are enabled. Various tasks associated with
different external interrupts and ISRs are as follows
(Fig. 11(a)).
1) When EOC of ADC (/INT1) occurs, the data of
all six channels are stored. The Start INS is set high.
The program returns from /INT 1 ISR.
2) When GPS read of FPGA (/INT0) occurs, the
data is read from the internal DPRAM within FPGA,
variable GPS available is set high and the program
returns.
In the main loop, INS and KF computations are
performed when Start INS bit and GPS available
are set high. A nine-state Kalman filter is applied to
combine the inertial solutions with the GPS position
and velocity errors in the inertial navigation solutions
[26]. In the present system nine states, namely, three
positions, three velocities, and three attitudes are used
in the Kalman filter. The emphasis of the work is
more on the real time hardware and programming
aspects related to the integration rather than the
TABLE I
Sensor Specifications used in Simulations
Quality
Value
Standard
Deviation
Scale factor of the accelerometer
250 mV/g §25=3 mV/g
Zero offset of the accelerometer
2500 mV §625=3 mV/g
Scale factor of the gyroscope
1.11 mV/± /s §10=3 %
–
Typical turn-on drift of the gyroscope
0.12 ± /s
Random noise incorporated in the GPS
–
§20 m
Kalman filter development. Sensor specifications used
in the simulation are given in Table I.
The actual implementation of the filter in the
program was done using a set of matrix functions
built on standard ANSI C routines. ANSI C is used
to aid in portability in case there is a need to use the
software on another platform.
IV. RESULTS AND DISCUSSIONS
As mentioned earlier the present paper describes
the real time hardware development for a typical
INS-GPS integration. The various hardware developed
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449
TABLE II
Memory Map of TMS320vc33
TABLE III
Computation Time for INS Parameters and Kalman Filter
Algorithm
Name
Origin
Length
Used
Words
ROM
RAM2
RAM3
MMRS
RAM0
RAM1
00000000
00800000
00804000
00808000
00809800
00809c00
000001000
000004000
000004000
000000100
000000400
000000400
00000120
00002F81
00000e18
00000000
00000400
00000000
4 K
16 K
16 K
Total words
16.58 K
1 K
are:
1) FPGA-based GPS data extractor which uses a
DPRAM for asynchronous data transmission.
2) Interface of FPGA and DSP.
3) ADC interfacing with DSP.
The complete hardware works on a single power
supply resulting in a compact system. It may be
noted that DSP TMS320VC33 does not have an
asynchronous serial communication port. To interface
GPS (which is an asynchronous device) with the DSP,
additional components are required. This could be
a microcontroller which will receive data from the
GPS and give output at the parallel interface. But the
microcontroller will remain highly underutilized in
this case. A USART can also be used, but in that case
the data sorting load will come on a DSP chip. Hence
using an FPGA is a good solution.
The proposed integrated system has been tested
by testing the individual blocks GIDAC and NPC.
Serial link GPS data is fed to FPGA and its output is
interfaced with NPC. Input for the system is read from
the data stored on the hard drive and the program
is run just as if the collection (of data) was taking
place in real-time. The simulated sensor data are
generated using trajectories obtained from flight
dynamic and control tool box (FDC) in MATLAB.
Different trajectories were obtained by giving step
and pulse inputs to elevator and ailerons. Aircraft
states were stored to simulate sensors. To analyze the
prediction accuracy of INS, it was compared with a
true trajectory generated using MATLAB.
From the simulation results obtained, as shown in
Table II, it was observed that the total memory usage
is about 17 K words out of the available 34 K words.
The DSP on the NPC card is operated at 75 MHz.
This corresponds to 26 nsec per instruction cycle and
hence the execution time is computed using this value.
On an average, each INS computation took about
1.17ms to execute on DSP (Fig. 12). Similarly, each
Kalman filter computation took around 6.33 ms, with
243461 instruction cycles, to execute on the DSP. One
cycle is of 26 nsec. Hence, dividing the total time by
the time taken by one cycle, we can find the total
number of cycles involved which comes out to be
243461. This is summarized in Table III.
450
Computation
During
No. of Cycles
Involved
Execution Time on DSP
Operated with 75 MHz
INS
Kalman Filter
Simultaneous
Sampling ADC
DPRAM access
44940
243461
–
1.17 ms
6.33 ms
10.4 ¹s
–
1 ¹s
Fig. 12. NPC timing requirement for INS and KF computations
tasks.
The bench tests were conducted in which the
simulated sensor inputs were fed into the proposed
integrated system and navigation results were
computed. These were found to be in agreement
with the simulated results. The developed integrated
GPS-INS system weighs about 183 g and consumes
1.7 W and 62 mW when the system is in active
and idle modes, respectively. The overall size of
the developed prototype system is 1500 £ 12:500 . For
verification of the results, MATLAB code developed
in [26] was used. Simulated results include various
errors in inertial sensors and the GPS. Same sensor
outputs were given to the present hardware and
the results were compared. The output waveforms
obtained from the integrated GPS-INS system are
shown in Figs. 13—15. Another example trajectory
(more complex than previous one) was simulated and
the flight data was fed into the DSP TMS320VC33.
The plots for latitude, longitude, and altitude obtained
directly from the hardware (DSP output) are shown in
Fig. 16. They show good agreement with the actual
trajectory.
V.
CONCLUSIONS
The paper discussed a new approach in acquiring
signals from IMU and GPS for a given Kalman filter
to fuse the data. A fast sampling ADC has been used
and interfaced with DSP. GPS data acquisition, using
the FPGA approach, reduced the chip count from 2 to
1 by implementing the UART and the DPRAM on the
FPGA chip itself. This provided an efficient interface
between the GPS and the DSP.
The prototype real-time integrated system based on
DSP lays the foundation for the development of future
systems of this type. As far as the time constraint and
the memory of the system is considered, the DSP
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2 APRIL 2009
Fig. 13. Distance along North in meters versus time.
Fig. 14. Distance along East in meters versus time.
Fig. 15. Altitude in meters versus time.
TMS320VC33 chosen as navigation processor has
an edge over other processors or COTS hardware.
Moreover, there is no requirement of any external
interface of RAM as the internal SRAM of the
processor is quite sufficient for computations. Present
filter used ¼ 50% of available memory and ¼ 60%
of the available computation time. Thus, the same
configuration can be used for a more complex filter
also. Overall, the prototype system developed operates
on a single power supply and consumes less power.
AGARWAL ET AL.: DESIGN AND DEVELOPMENT OF A REAL-TIME DSP AND FPGA-BASED
451
Fig. 16. DSP (hardware) output. (a) Latitude versus time
(x-axis = 0:01 s/data sample). (b) Longitude versus time
(x-axis = 0:01 s/data sample). (c) Altitude versus time
(x-axis = 0:01 s/data sample).
Two example trajectories were considered to test the
developed system. The results obtained for the first
example trajectory are found to be in close agreement
with the actual trajectory. For the second trajectory,
both the maximum error and standard deviation of
error are observed to be higher.
452
Fig. 17. Plots with GPS outage from 100 to 105 s. (a) Latitude
versus time. (b) Longitude versus time; (c) Height versus time.
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 45, NO. 2 APRIL 2009
From the test results over a span of 300 s, it is
observed that after initialization, the position accuracy
of GPS-INS system is comparable to that of the
GPS receiver. It must be noted that the output of
the Kalman filter is bounded by the GPS output.
Trajectory plots (for the first example) showing a GPS
“outage” and its effect are shown in Fig. 17. If more
Kalman filter states are considered, the GPS outages
can be handled better.
[10]
[11]
[12]
ACKNOWLEDGMENT
The authors would like to thank Prof. K. Sudhakar,
Mr. Vikas Kumar Naresh, Mr. Lalit Saptarshi, and
Mr. Chetan Patki, all from IIT-Bombay, for their help
during the course of this work.
[13]
[14]
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Vivek Agarwal (M’93–SM’01) received a bachelor’s degree in physics from
St. Stephen’s College, Delhi University. He then obtained an integrated master’s
degree in electrical engineering from the Indian Institute of Science, Bangalore,
India. Subsequently, he pursued a Ph.D. degree in the dept. of Electrical and
Computer Engineering, University of Victoria, Canada.
After completing the Ph.D. degree in 1994, he briefly worked for Statpower
Technologies, Burnaby, Canada as a research engineer. In 1995 he joined the
Department of Electrical Engineering, Indian Institute of Technology–Bombay,
India, where he is currently a professor. His main areas of interest are power
electronics and electronic systems. He works on the modeling and simulation
of new power converter configurations, intelligent and hybrid control of power
electronic systems, power quality issues, EMI/EMC issues, and conditioning of
energy from nonconventional energy sources. He is a Fellow of IETE and a life
member of ISTE.
Hemendra Arya received the M.Tech. and Ph.D. degrees from IIT-Bombay,
India, in 1991 and 1997, respectively, from the Aerospace Engineering
Department.
He is currently an assistant professor with the Department of Aerospace
Engineering, IIT-Bombay. He is actively involved in modelling and simulation
activities related to mini and micro aerial vehicles. His research interests are
autonomous aerial vehicles and sensor fusion related to these.
Bhaktavatsala Shivaram was born in Bangalore, India, on February 1, 1973. He
received the Bachelor’s Eng. degree in 2001 from Bangalore University, and the
Master’s degree in electronic systems in 2004 from IIT-Bombay, India.
He started his professional career from 1991 after his Diploma in Electronics
and Telecommunication Eng. from Board of Technical Education, Bangalore.
From 1991 to 1998 he was with BPL SANYO Ltd, as assistant technical officer
in the Consumer Electronics Research and Product Group. From May 1998
to 2006 he was with the Aeronautical Development Establishment, engaged
in research and new product development in the field of electronic systems
development based on single board computers for flight control computers.
Currently he is an electrical design engineer at KLA-Tencor Software India Pvt
Ltd, Chennai, engaged in research and new product development of electronic
systems for semiconductor wafer inspection tools. His current research lies in the
field of embedded, low cost, highly reliable compact systems.
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