White Paper
Pin Assignment & Analysis
Using the Quartus II Software
Today’s FPGAs support multiple I/O standards and have large pin counts. Designers
must be able to efficiently create pin assignments for designs in these advanced devices.
Designers also need the ability to easily check the legality of the pin assignments to
ensure that the pin-out is not violating any board layout rules such as pin spacing, current
limitations, etc.
Time to market constraints means board layout development must be done in parallel
with, or even prior to, designing the FPGA. Therefore, checking the legality of I/O
assignments without a design or with a partially completed design is a design
requirement.
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Altera has introduced the Start I/O Assignment Analysis command in the Quartus II
software version 3.0 to meet this design requirement. This new command quickly and
thoroughly checks the legality of pin assignments, with or without a design file. This
command can perform in-depth checks of a design’s I/O pins and surrounding logic
against various requirements ranging from proper VREF usage, pin location assignments,
and mixing of various I/O standards.
This white paper describes the design flow to assign and analyze pin-outs using the Start
I/O Assignment Analysis command with and without a complete design.
Assigning & Analyzing Pin-outs Design Flows
The pin assignment and analysis flow depends on the FPGA design status when using the
Start I/O Assignment Analysis command.
„ When the board layout must be complete prior to starting the FPGA design, use the
flow shown in Figure 1. This flow does not involve any design files and is used to
check the legality of pin assignments.
„ When a design is complete or partially complete, use the flow shown in Figure 3 on
page 4. This flow uses design files.
Both flows involve creating pin assignments, running the analysis, and reviewing the
report file. These flows currently support StratixTM, Stratix GX, and CycloneTM FPGAs.
June 2003, ver. 1.0
WP-QIIPNASGN-1.0
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Pin Assignment & Analysis Using the Quartus II Software
Altera Corporation
Design Flow without Design Files
During the early stages of development of an FPGA device, board layout engineers may
request preliminary or final pin-outs. With the Assignment Editor, tool command
langauge (Tcl) scripting, or by directly editing the the complier settings file (.csf),
designers can create pin related assignments like locations and I/O standards for the
FPGA design. The Start I/O Assignment Analysis command checks on the legality of
these assignments.
Figure 1. Assigning & Analyzing Pin-outs without Design Files
Quartus II project (.quartus)
Create pin-related assignments
.csf, .esf
Start I/O assignment analysis
Modify and correct illegal
assignments found in report file
Report file generated
To assign and analyze pin-outs using the I/O Assignment Analysis command without
design files:
1. Create a Quartus II project and select the target device.
2. Make pin assignments. Because there are no design files, pin-related assignments
(I/O standards, toggle rate, current strength, etc.) can be made to reserved pins
using the Assignment Editor or with the Tcl scripting interface. See the Creating
I/O Assignments section of this document.
3. Run the Start I/O Assignment Analysis command and view the report file.
4. Correct any errors reported by the I/O assignment analysis and re-run the
analysis.
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Pin Assignment & Analysis Using the Quartus II Software
Design Flow with Design Files
In this flow, run the Start I/O Assignment Analysis command before a full compilation.
During a full compilation, illegal pin assignments are not found until the fitter stage of a
compilation. Because the errors are reported during fitting, errors are not caught quickly.
By running the Start I/O Assignment Analysis command before full compilation, any
incorrect pin assignments are reported within minutes. The I/O assignment analysis takes
on average less than one minute compared to compilation, which can take hours. Figure 2
illustrates saving compilation time with the Start I/O Assignment Analysis command.
Figure 2. Saving Compilation Time with the Start I/O Assignment Analysis
Command
Error reported and fixed
Full compilation
Full compilation
Full compilation
I/O
assignment
analysis
Error
reported
and fixed
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Pin Assignment & Analysis Using the Quartus II Software
Altera Corporation
Figure 3. Assigning & Analyzing Pin-outs with Design Files
Quartus II project (.quartus)
Design files .edf, .vqm, .v, .vhd, .bdf
Create pin-related assignments
.csf, .esf
Analysis and synthesis
Mapped netlist
Start I/O assignment analysis
Report file generated
Modify and correct illegal
assignments found in report file
Back annotate I/O assignment
analysis pin placements
To assign and analyze pin-outs using the Start I/O Assignment Analysis command with
design files:
1. Create a Quartus II project and design files.
2. Create pin-related assignments with the Assignment Editor or the Tcl interface. Pin
related assignments include I/O standards, toggle rate, current strength, termination
type, etc. Pin location assignments can also be created by dragging and dropping pins
from the node finder to the floorplan editor.
3. Analyze and synthesize the design to generate the internal mapped netlist.
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Pin Assignment & Analysis Using the Quartus II Software
4. Run the Start I/O Assignment Analysis command. This command was designed to be
used frequently. The time it takes to run is in the range of seconds and minutes.
5. The analysis should be performed repeatedly until there are no errors found.
However, if there are changes to the PLLs, LVDS blocks, gigabit transceiver blocks
(GXBs), or pin assignments in the design, then running this command before a full
compilation is highly recommended.
6. Correct and rerun the analysis after the errors have been identified in the generated
analysis report. The report includes a pin-out file and a list of resource usage along
with the errors.
Inputs Used for I/O Assignment Analysis
I/O assignments are stored into settings files that are read into the Start I/O Assignment
Analysis command along with the mapped netlist, if the second flow is used.
With Quartus II software version 3.0, there are many ways to create pin-related
assignments as well as new types of assignments like assigning pins to I/O banks device
edges.
Creating I/O Assignments
Creating I/O assignments can be cumbersome and may require a great deal of time from
the designer. To satisfy designer preferences and help designers efficiently create these
assignments, Altera provides three methods for creating I/O pin assignments:
„ The Assignment Editor
„ Tcl scripts
„ Drag and drop capability for nodes from the node filter to the floorplan editor
Types of I/O pin assignments include various I/O standards, current strengths, on-chip
termination settings, timing constraints, etc.
All pin related assignments are stored in the .csf or .esf file and are read into the Start I/O
Assignment Analysis command.
For more information on using the Assignment Editor with the Quartus II software, refer
to the Using the Assignment Editor in the Quartus II Software white paper.
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Pin Assignment & Analysis Using the Quartus II Software
Altera Corporation
Location Assignments
A new feature in the Quartus II software version 3.0 is the ability to assign pins to banks
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and edges. Altera devices have numerous I/O banks available, and it is common to see a
group of pins (buses) with compatible I/O standards placed into a particular bank or
banks.
Edges of a chip can also be used as a placement location. For example, in Stratix devices,
all differential high-speed I/O pins are located on the left and right edges of the device.
Assigning pins to edges is ideal for making LVDS pin location assignments where exact
pin location is flexible. Figure 4 shows the Altera device package edges.
Figure 4. Package View of the Four Edges on an Altera Device
Top Edge
Left Edge
Right Edge
Bottom Edge
Assignments with the Floorplan Editor
Another method of making pin assignments, in addition to the Assignment Editor and the
Tcl interface is through the Floorplan Editor. To access the Floorplan Editor Timing
Closure Floorplan choose Timing Closure Floorplan (Assignments menu).
With the Timing Closure floorplan, the designer can toggle between the package view
and the interior detailed view. In both views the designer can drag and drop pins from the
node finder or a block diagram file (.bdf) into a desired pin or bank in the Floorplan
Editor. See Figure 5.
The Floorplan Editor is a great way to create pin assignments as the designer can see
where the pins will be located without having to reference the pin package
documentation.
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Pin Assignment & Analysis Using the Quartus II Software
Figure 5. Creating Pin Location Assignments with the Node Finder & the Timing
Closure Floorplan Editor.
Generating a Mapped Netlist
A mapped netlist is only required in the flow shown in Figure 3 for saving compilation
times with the Start I/O Assignment Analysis command. The internal netlist is used to
identify what the pin names are and their direction (input, output, bidirectional) and is
used during the I/O analysis to perform a thorough check.
The mapped netlist can be generated by running the analysis and synthesis command in
the Quartus II software. Analysis and synthesis can be executed from the Quartus II menu
or with the quartus_map executable.
The mapped netlist generated is stored internally in the Quartus II database (\db)
directory.
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Pin Assignment & Analysis Using the Quartus II Software
Altera Corporation
Running the I/O Assignment Analysis
The Start I/O Assignment Analysis command runs legality checks on the user pin-outs,
similar to the checks done in the fitter stage, as well as the surrounding logic which
directly feeds or is fed by pins.
The Start I/O Assignment Analysis command with the flow in Figure 3 can only perform
simple checks, including placement and I/O standards, with the user pin-outs.
The flow in Figure 3 suggests running the I/O assignment analysis any time a change is
made to the pin assignments of the design before executing a full compilation. The
analysis checks all the pin assignments and surrounding logic for illegal assignments,
e.g., the pad spacing requirements between different I/O standards are violated. These
checks may include if the pin location supports the I/O standard assigned, a legal current
strength, supported VREF voltages, or if the PCI diode is allowed.
Besides the I/O pins, the Start I/O Assignment Analysis command also checks blocks that
directly feed or are fed by a pin such as PLLs, LVDS, and GXB blocks. For example, this
command checks that the pin assignment for a PLL input can feed a PLL capable of
operating at the specified frequency. In Stratix devices different PLLs and I/O banks have
different capabilities, so it is important to select valid pins.
The Start I/O Assignment Analysis command can be executed from the Quartus II
software menu (see Figure 6) or from the command prompt. Run the command by
choosing Start > Start I/O Assignment Analysis (Processing menu).
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Pin Assignment & Analysis Using the Quartus II Software
Figure 6. Running the I/O Assignment Analysis Command from the Quartus II
Software Menu
To run the Start I/O Assignment Analysis command from a command prompt type in the
followiing text and press Enter:
quartus_fit <project-name> --check_ios
When running this command, the fitter’s previous compilation results are overwritten.
Any other results, such as analysis and synthesis or timing analysis, are not affected.
Understanding the I/O Assignment Analysis Report
The report file generated from runnng the Start I/O Assignment Analysis command
provides a detailed summary of the I/O assignments in the project. The report file follows
the format similar to the compilation report. See Figure 7.
In the resource section, a summary of all the input, output, and bidirectional pins and
their placement are available. There is also a floorplan view for reference.
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Pin Assignment & Analysis Using the Quartus II Software
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Figure 7. Summary of the I/O Bank Usage in the I/O Assignment Analysis Report
Suggested & Partial Placement
Along with the design’s fixed I/O assignments, there may be I/O pins that the designer
has not assigned to a particular pin.
For example, a designer may run the I/O assignment analysis with a group of LVDS pins
assigned to an edge (left or right for high-speed differential I/Os). The I/O assignment
analysis performs the legality checks and also provide a suggested pin placement for the
LVDS pins within the edge.
The suggested placement made by the analysis can then be reviewed in the pin-out file
and in the resource section of the report file.
To accept the suggested pin locations from the I/O assignment analysis, the designer can
use the back annotation option. The back annotation feature saves pin and device
assignments into the settings file that can be viewed later with the Assignment Editor.
Detailed Error/Status Messages
One of the key features about the report file are the detailed messages. Incorrect I/O
assignment errors have detailed messages indicating the node in question as well as a
description of the problem. These detailed messages help the designer locate and fix the
reported problem.
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Pin Assignment & Analysis Using the Quartus II Software
The designer can highlight the message and use the right mouse button to select Message
Locations to locate the node in the Assignment Editor, source file, compilation report or
the timing closure floorplan to help understand and resolve the problem.
The messages displayed by the I/O assignment analysis are much more detailed than the
fitter messages in earlier versions of the Quartus II software. The detailed messages can
be found in the Fitter Message section of the report file as well as the Processing tab in
the messages window by choosing Utility Windows->Messages (View menu).
Figure 8 is an example of an error message that the I/O assignment analysis reports.
Figure 8. Example of Error Messages Reported by I/O Assignment Analysis
Conclusion
The Quartus II software version 3.0 provides designers with the capabilities to efficiently
create pin assignments and to quickly and thoroughly validate the legality of the
assignments. These capabilities can help reduce development time by catching illegal pin
and surrounding logic assignments early in the design cycle without long design
compilations.
By providing the designer with more confidence in the current design pin-outs, board
layout engineers can work in parallel with FPGA designers to provide a shorter time-to
market for their product.
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Pin Assignment & Analysis Using the Quartus II Software
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