Application Note NCS018
July 2000
A Basic Controller for the CIDR Co-Processor™ Longest Prefix Match Engine
Introduction
The NL77542 CIDR Co-Processor™ Longest Prefix Match Engine is a table lookup engine optimized for
the Longest Prefix Match search algorithm used in Classless Inter-Domain Routing (RFC1519). By
performing one LPM search per clock cycle at speeds up to 66 MHz, the NL77542 easily handles
multiple OC-192 or 10G Ethernet channels. In addition, it provides the ability to simply and easily update
the forwarding table at clock speed without sorting, thus maintaining coherency with associated data at
all times. Virtually any application that performs Layer 3 forwarding of IPv4 packets can use the
NL77542 to speed up the critical path in making routing decisions.
This application note documents a controller reference design for single or cascaded NL77542 CIDR CoProcessors, which is available as Verilog code.
Features
Features of the CIDR Co-Processor controller reference design include:
•
•
•
•
•
Full ability to add and delete entries
IPv4 Longest Prefix Match and Exact Match Search capability
Separate data input and result ports
Easy-to-learn microinstruction set
Tag port allows the user to assign a 4-bit tag to each search and allow the controller to keep
track of the searches
Block Diagram
40
5
24
DAT A_I N[ 39: 0]
PREFIX_IN[4:0]
PBUS[39:0]
PFXBUS[4:0]
RBUS[23:0]
INDEX_OUT[23:0]
40
5
24
PBUS[39:0]
PFXBUS[4:0]
RBUS[34:30]
RBUS[18:0]
INDEX_VALID
/FF
IBUS[11:0]
4
4
4
2
12
IBUS[11:0]
TAG_IN[3:0]
TAG_OUT[3:0]
NFABUS[23:0]
24
NFABUS[23:0]
INSTRUCTION[3:0]
OPTION[1:0]
/MF
/RESET
/MF
/MMF
/MMF
/EMF
/EMF
/CE
/FF_IN
CLK
/RESET_OUT
/FF
/CS
/RESET
Controller
CLK
NL77542 CIDR Co-Processor™
Note: RBUS[34:30] must be pulled high with external pull-up resistors (not shown)
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Subject to change without notice
A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
Pin Descriptions
Signal Name
DATA_IN[39:0]
PREFIX_IN[4:0]
INDEX_OUT[23:0]
INDEX_VALID
TAG_IN[3:0]
TAG_OUT[3:0]
I/O
Type
I
I
O
O
I
O
INSTRUCTION[3:0
]
OPTION[1:0]
/FF
I
I
O
PBUS[39:0]
PFXBUS[4:0]
RBUS[23:0]
IBUS[11:0]
NFABUS[23:0]
/MF
/MMF
/EMF
/FF_IN
/CE
CLK
/RESET
/RESET_OUT
O
O
I
O
I
I
I
I
I
I
I
I
O
Description
Input write or search data from host system
IPv4 address prefix length input from host system
Outputs search results or NFA
Result latch enable output
4-bit tag input
Tag output; returns the tag of the search which is being
returned
Microinstruction input
Option field for certain microinstructions
Active-low full flag output indicates that the address table
is full
PBUS output to CIDR Co-Processor cascade
PFXBUS output to CIDR Co-Processor cascade
RBUS input from CIDR Co-Processor cascade
IBUS output to CIDR Co-Processor cascade
NFABUS input from CIDR Co-Processor cascade
/MF input from CIDR Co-Processor cascade
/MMF input from CIDR Co-Processor cascade
/EMF input from CIDR Co-Processor cascade
/FF input from CIDR Co-Processor cascade
Active low chip enable
System clock
Asynchronous controller reset input
Asynchronous reset output to CIDR Co-Processor cascade
Instruction Set Summary
Instruction
Invalid opcode
Write to Routing Table
Write to Global Mask Register
Read Next Free Address
Search
Search using Global Mask
Delete
Set Exact Match Mode
Set Longest Prefix Match Mode
Set Full Flag
Write to Device ID Register
Software Reset
Select Single Device Mode
Select Global Mode
Invalid opcode
Invalid opcode
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Opcode
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Subject to change without notice
A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
Command Descriptions
Write to Routing Table
Opcode: 0x1
Description: Writes the route entry on DATA_IN[39:0] to the CIDR Co-Processor cascade at the Next
Free Address, using the value on PREFIX_IN[4:0] to specify the prefix length of the route.
The user must set the controller into Global Mode before executing this instruction if
multiple NL77542 devices are cascaded.
Write to Global Mask Register
Opcode: 0x2
Description: Writes the value on DATA_IN[39:0] to the Global Mask Register of the CIDR Co-Processor
cascade. The Global Mask Register used is specified by the OPTION field (OPTION[1:0]).
The user must set the controller into Global Mode before executing this instruction if
multiple NL77542 devices are cascaded.
Read Next Free Address
Opcode: 0x3
Description: Returns the Next Free Address on INDEX_OUT[23:0]; this is the address at which new
entries written to the routing table will be stored. The user must set the controller into
Global Mode before executing this instruction if multiple NL77542 devices are being
controlled. NFA reads take precedence over search results; if a search returns its results
on the same cycle that INDEX_OUT is driven by an NFA read, the search result will be
discarded.
Search
Opcode: 0x4
Description: In Longest Prefix Match mode, performs the Longest Prefix Match search operation and
returns the results 8 clock cycles later on INDEX_OUT[23:0]. The search key is latched
from DATA_IN[39:0]. The user must set the controller into Global Mode before executing
this instruction if multiple NL77542 devices are cascaded.
In Exact Match Mode, performs an Exact Match search operation and returns the results 6
clock cycles later on INDEX_OUT[23:0]. The search key is latched from DATA_IN[39:0],
and the prefix is latched from PREFIX_IN[4:0]. To match, an entry must match both the
key and the prefix exactly. The user must set the controller into Global Mode before
executing this instruction if multiple NL77542 devices are cascaded.
Search using Global Mask
Opcode: 0x5
Description: In Longest Prefix Match mode, performs the Longest Prefix Match search operation using
the global mask specified in OPTION[1:0] and returns the results n cycles later on
INDEX_OUT[23:0]. The search key is latched from DATA_IN[39:0]. The user must set the
controller into Global Mode before executing this instruction if multiple NL77542 devices
are cascaded.
In Exact Match Mode, performs an Exact Match search operation using the global mask
specified in OPTION[1:0] and returns the results n cycles later on INDEX_OUT[23:0]. The
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Subject to change without notice
A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
search key is latched from DATA_IN[39:0], and the prefix is latched from PREFIX_IN[4:0].
To match, an entry must match both the key and the prefix exactly. The user must set the
controller into Global Mode before executing this instruction if multiple NL77542 devices
are cascaded.
Delete
Opcode: 0x6
Description: Deletes all matching entries. Used in conjunction with an Exact Match search to select and
delete entries based on their values. The user must set the controller into Global Mode
before executing this instruction if multiple NL77542 devices are cascaded.
Select Exact Match Mode
Opcode: 0x7
Description: Places all devices into Exact Match Mode. The user must set the controller into Global
Mode before executing this instruction if multiple NL77542 devices are cascaded.
Select Longest Prefix Match Mode
Opcode: 0x8
Description: Places all devices into Longest Prefix Match mode. The user must set the controller into
Global Mode before executing this instruction if multiple NL77542 devices are cascaded.
Set Full Flag
Opcode: 0x9
Description: Sets the CIDR Co-Processor’s Full Flag. Used in the initialization sequence detailed in the
Applications Information section.
Write to Device ID Register
Opcode: 0xA
Description: Writes to the CIDR Co-Processor’s Device ID with the data on DATA_IN[3:0]. Used in the
initialization sequence detailed in the Applications Information section.
Software Reset
Opcode: 0xB
Description: Resets the CIDR Co-Processor’s internal registers and routing tables. Used in the
initialization sequence detailed in the Applications Information section.
Select Single Device Mode
Opcode: 0xC
Description: Puts the CIDR Co-Processor controller and cascade into single device mode. Used in the
initialization sequence detailed in the Applications Information section.
Select Global Mode
Opcode: 0xD
Description: Puts the CIDR Co-Processor controller and cascade into global mode. Used in the
initialization sequence detailed in the Applications Information section.
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Subject to change without notice
A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
Applications Information
Modes of Operation
The CIDR Co-Processor controller core operates in one of two user-selectable searching modes. In the
Longest Prefix Match mode, the controller will return the longest prefix match. This is the default mode,
and is used primarily for performing packet forwarding. In the Exact Match mode, the controller will
return any entries that match the search key exactly (both data and prefix). This mode is used to mark
routing entries for subsequent deletion from the table.
The CIDR Co-Processor controller core also supports two modes of operation for cascaded devices. The
single device mode allows the user to target a particular device for subsequent commands. The device
is selected based on the device ID written during the initialization process. The global mode eliminates
this restriction and allows all cascaded devices to respond to commands.
Registered Inputs and Outputs
All inputs and outputs of the CIDR Co-Processor controller core are registered, including the Chip Enable
line. This gives the design the flexibility to be integrated with customer-specific code without creating
timing problems due to the place and route. All inputs and outputs are referenced to the rising edge of
the clock.
Chip Enable and Pipelining
The active-low Chip Enable line controls whether data and instructions will be latched into the core for
each clock cycle, but does not affect the output signals (Index Out as well as the flags). This is to ensure
that deasserting the Chip Enable line will not stop or stall the pipeline. Result data will continue to be
output from the core until the pipeline has been flushed.
Initialization
Before the CIDR Co-Processor and controller can be used, the user must perform the initialization
sequence detailed below:
1. Assert the Reset input of the controller for 64 clock cycles
2. After bringing the controller out of reset, wait at least one clock cycle before accessing the
device
3. Write to the first device’s ID register with a value of 0x0
4. If this is a single device (no cascade), go to step 8
5. Execute the Set Full Flag instruction
6. Write to the next device’s ID register, incrementing the previous device’s ID value by 1
7. If there are more devices in the cascade, go to step 5
8. Execute a software reset
9. Wait one clock cycle
10. The controller and CIDR Co-Processor cascade is now properly configured and ready for normal
operation
Adding Entries
Entries are always added to the Next Free Address. This address is continuously made available
through the Next Free Address outputs of the CIDR Co-Processor, and can be accessed through the
Read NFA command of the controller core. The following steps outline the procedure for adding a route
to the forwarding table:
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A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
1. Read the Next Free Address
2. Update the associated data memory with the routing information (e.g. next-hop route)
3. Execute the command Write to Routing Table.
Searching Entries
For searches designed to forward packets, the user must set the controller in Longest Prefix Match mode
by executing the Select Longest Prefix Match Mode instruction.
The controller performs searches and returns the results in the order that they are issued. The user may
optionally present a 4-bit tag to the controller along with data for a search. The controller will
automatically return that tag along with the results for that search, thus offloading the task of keeping
track of the search order to the controller.
The user may also perform an Exact Match search by setting the controller in Exact Match mode. This
mode compares the data on DATA_IN against the data in the NL77542 array and the prefix length input
on PREFIX_IN against the prefix data in the array, and returns only entries that exactly match the search
key. This type of search is used primarily for managing entries (determining if a particular entry exists in
the array) or in marking entries for deletion.
Deleting Entries
The Delete command will delete all entries that matched the last search preceding the Delete command.
In order to maintain full control over which entry is being deleted, this search should be an Exact Match
search. A Longest Prefix Match search may result in unpredictable deletion of entries, as an entire
aggregated route or a default route may be marked for deletion.
NetLogic Microsystems, Inc.
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Subject to change without notice
A Basic Controller for the CIDR CoProcessor™ Longest Prefix Match Engine
Application Note
NCS018
Summary
A simple, fast controller for the CIDR Co-Processor has been outlined that enables users to speed the
design of IPv4 packet forwarding engines. This controller code provides a base that users can use to
develop interfaces to microprocessors, network processors, or other interfaces such as PCI or internal
data paths within the programmable logic device of their choosing.
For additional information, contact your NetLogic Microsystems representative or the following:
INTERNET:
http://www.netlogicmicro.com
EMAIL:
Sales: sales@netlogicmicro.com
Technical Support: support@netlogicmicro.com
Worldwide Headquarters:
465 Fairchild Dr., Suite 101, Mountain View, CA 94043
1.650.961.6676
CIDR Co-Processor™ and NetLogic Microsystems™ are trademarks of NetLogic Microsystems, Inc.
All other trademarks are the property of their respective owners.
The information contained herein is the property of NetLogic Microsystems, Inc., and is believed to be accurate at the time of printing. NetLogic
assumes no liability for any error or omissions in this information, or for the use of this information or products described herein. NetLogic reserves the
right to make changes to its products at any time to improve reliability, functionality, performance, or manufacturability. Disclosure of the information
herein does not convey a license or any other right in any patent, trademark, or other intellectual property of NetLogic.
Copyright © 2000 NetLogic Microsystems, Inc.
All Rights Reserved
Printed in the U.S.A.
July 2000
NCS018