EPXA10
DDR Development Board
Hardware Reference Manual
April 2003
Version 1.3
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
MNL-EXCDDRDEVBRD-1.3
Excalibur EPXA10 DDR Development Board Hardware Reference Manual
Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services. All rights reserved.
ii
Altera Corporation
About this Manual
This manual provides comprehensive information about the Altera®
EPXA10 DDR development board.
Table 1 shows the manual revision history.
Table 1. Revision History
Date
How to Find
Information
April 2003
Improved expansion header tables.
January 2003
Amended EPC16 configuration device section.
December 2002
Changed board device number.
November 2002
First publication.
■
■
■
■
Altera Corporation
Description
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click on the binoculars icon in the top toolbar to open the
Find dialog box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this Manual
EPXA10 DDR Development Board Hardware Reference Manual
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
Table 2. How to Contact Altera
Information Type
Altera Literature
Services
Access
Electronic mail
Non-technical
Telephone hotline
customer service
Fax
Technical support Telephone hotline
Fax
General product
information
USA & Canada
All Other Locations
lit_req@altera.com (1)
lit_req@altera.com (1)
(800) SOS-EPLD
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7606
(408) 544-7606
(800) 800-EPLD
(7:00 a.m. to 5:00 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-6401
(408) 544-6401 (1)
World-wide web site http://www.altera.com/mysupport
http://www.altera.com/mysupport
FTP site
ftp.altera.com
ftp.altera.com
Telephone
(408) 544-7104
(408) 544-7104 (1)
World-wide web site http://www.altera.com
http://www.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Typographic
Conventions
About this Manual
The Excalibur EPXA10 DDR Development Board Hardware Reference Manual
uses the typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Quartus II Help topics are
shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device
with the BitBlaster™ Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
Altera Corporation
v
Notes:
Contents
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
Features .............................................................................................................................................9
Functional Overview .....................................................................................................................10
Board Components ........................................................................................................................10
Interfaces .........................................................................................................................................14
PCI Interface ...........................................................................................................................14
10/100 Ethernet Parallel Interface .......................................................................................16
Serial I/O Interfaces ..............................................................................................................18
Memory Interfaces .................................................................................................................19
LED & Switch Interfaces .......................................................................................................22
Trace Port Interface ................................................................................................................26
10-Pin IDC Header Interface ................................................................................................26
Expansion Header Interface .................................................................................................27
Jumper Configuration ...................................................................................................................32
Clocks ...............................................................................................................................................35
CLK_REF & the FPGA Clocks ..............................................................................................37
MAX 3032 ................................................................................................................................38
Embedded Stripe Clocks .......................................................................................................38
Jumper Configuration for the Clock Input .........................................................................40
Sources for the EPXA10 Clocks ............................................................................................40
Device Configuration ....................................................................................................................41
Booting from Flash Memory ................................................................................................41
Configuring Using the EPC16 ..............................................................................................42
Configuring Using JTAG ......................................................................................................43
Configuration Schemes .........................................................................................................44
Debugging Features .......................................................................................................................44
Third-Party Debugging Tools ..............................................................................................45
JTAG Interfaces ......................................................................................................................45
Power Supply .........................................................................................................................47
Test Points .......................................................................................................................................51
Signals ..............................................................................................................................................52
UART .......................................................................................................................................52
PCI ............................................................................................................................................53
Trace Port ................................................................................................................................54
Configuration/Debugging Interfaces .................................................................................55
Pin-Outs ...........................................................................................................................................57
Configuration .........................................................................................................................57
Altera Corporation
vii
Contents
EPXA10 DDR Development Board Hardware Reference Manual
DDR SDRAM Interface .........................................................................................................59
EBI ............................................................................................................................................61
PCI ............................................................................................................................................63
UART1 & UART2 ...................................................................................................................64
Ethernet ...................................................................................................................................64
Fast I/O Pins ...........................................................................................................................65
User LEDs, Switches & Push Button Switches ..................................................................65
Trace Port ................................................................................................................................66
IDC 10-Pin Header .................................................................................................................66
Expansion Header ..................................................................................................................67
General Usage Guidelines ............................................................................................................74
Anti-Static Handling ..............................................................................................................74
Power-Up ................................................................................................................................74
Power Consumption ..............................................................................................................74
PCI Cards ................................................................................................................................74
Unused EPXA10 Device Pins ...............................................................................................75
Test Core Functionality .........................................................................................................75
viii
Altera Corporation
EPXA10 DDR Development
Board
■
■
Powerful development board for embedded processor FPGA designs
–
Features an EPXA10F1020C1 device
–
Supports intellectual property-based (IP-based) designs using a
microprocessor
Industry-standard interconnections
–
10/100 megabits per second (Mbps) Ethernet with full and half
duplexing
–
Two 32-bit peripheral component interconnect (PCI) connectors
1
■
■
■
■
■
■
■
■
Altera Corporation
These features require additional IP blocks; contact Altera
for further details.
–
Two RS-232 ports
Memory subsystem
–
32-Mbyte flash memory
–
128-Mbyte DDR SDRAM
Multiple clocks for communications system design
Multiple ports for configuration and debugging
–
IEEE Std. 1149.1 Joint Test Action Group (JTAG)
–
Support for configuring the EPXA10 device using flash memory,
an EPC16, or a MasterBlaster™ or ByteBlasterMV™ cable
Expansion headers for greater flexibility and capacity
–
Four expansion headers for daughter-card access
–
3.3-V/5-V/12-V/–12-V expansion/prototype headers to
support up to 502 user I/O pins
Two PCI connectors accommodate 3.3-V and universal PCI
expansion cards
Additional user-interface features
–
One user-definable 9-bit dual in-line package (DIP) switch block
–
Four user-definable push-button switches
–
Eight user-definable LEDs
–
One IDC plug—10 pins 2.54 mm pitch, with 8 user-definable
connection and two power and ground pins
Test points provided to facilitate system development
Trace port connections
9
Specifications
Features
1
EPXA10 DDR Development Board Hardware Reference Manual
Functional
Overview
Designers can use the EPXA10 DDR development board as a desktop
development system. It provides a hardware platform to start developing
embedded systems immediately; and delivers clocks, debugging, and
trace facilities to support the system under development in an Excalibur™
EPXA10 device.
The EPXA10 DDR development board provides a flexible, powerful
debug and development environment. Designers can use the board for a
variety of purposes, including building and emulating systems for special
requirements, and conducting trace and debug investigations.
Board
Components
10
This section introduces a brief overview of the components of the EPXA10
DDR development board, which is shown in Figure 1 on page 11.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 1. EPXA10 DDR Development Board Layout
290 mm
Clocks. For
greater
detail, see
Figure 11
on page 37
Power
supply. For
greater
detail, see
Figure 15
on page 48
290 mm
Altera Corporation
11
EPXA10 DDR Development Board Hardware Reference Manual
The EPXA10 DDR development board features the largest member of the
Excalibur family, the EPXA10. The EPXA10 features an integrated
microprocessor system with the APEX 20KE architecture in a 1,020-pin
FineLine BGA™ package.
Table 1 lists the main features of the device.
Table 1. EPXA10 Device Features
Feature
Capacity
Maximum system gates
1,772,000
Typical gates
1,000,000
LEs
38,400
ESBs
160
Maximum RAM bits
327,680
Maximum macrocells
2,560
Maximum user I/O pins
521
In addition, the EPXA10 provides a variety of peripherals, as listed in
Table 2. .
Table 2. EPXA10 Device Peripherals
Peripheral
Description
ARM922T 32-bit RISC processor
For speed grade –1: up to 200 MHz
For speed grade –2: up to 166 MHz
For speed grade –3: up to 133 MHz
ETM9 trace module
Used for software debugging
Interrupt controller
Used for the interrupt system
Internal single-port SRAM
256 Kbytes
Internal dual-port SRAM
128 Kbytes
SDRAM controller
Interfaces between the internal system bus and SDRAM
External DDR SDRAM
Refer to the Excalibur Devices Hardware Reference Manual for details of
supported sizes
Expansion bus interface (EBI)
Interfaces to flash memory
External flash memory
Refer to the Excalibur Devices Hardware Reference Manual for details of
supported sizes
Watchdog timer
Protects the system against software failure
UART
Facilitates serial communication
Reset controller
Resets the device
12
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
f
Refer to the Excalibur Devices Hardware Reference Manual for details about
EPXA10 devices.
Figure 2 illustrates the relationship between the EPXA10 device and the
development board peripherals.
Figure 2. EPXA10 DDR development Board Block Diagram
DDR
SDRAM
Excalibur
EPXA10
Flash
Memory
External
Connectors
Configuration
UART
Connectors
PCI
Connectors
Altera Corporation
Ethernet
Connector
13
EPXA10 DDR Development Board Hardware Reference Manual
Interfaces
Table 3 lists the interfaces on the EPXA10 DDR development board..
Table 3. Development Board Interfaces
Interface
Description
PCI connectors
The connectors operate at 32-bit, 33 MHz and can be used by designers to connect
standard, commercially-available 3.3-V (only) and universal PCI cards
10/100 Ethernet with fulland half-duplexing
This interface consists of a connector, transceiver and transformer. The MAC is
implemented in the Altera device as an IP block. The connection between the MAC
and the transceiver is a standard MII
IEEE Std. 488 RS-232
serial interfaces
This interface is a 12.0-V transceiver with 235-kbps data rate in a TSSOP package
Debugging/programming
ports
The board supports in-circuit debugging by means of the MasterBlaster,
ByteBlasterMV, or Multi-ICE cables
MICTOR connector
This connector provides debugging facilities for the trace port
10-pin IDC connector
Facilitates access to the user I/O
Expansion headers
These connectors allow designers to stack multiple daughter boards as required
User I/O pins
The expansion header provides up to 502 user I/O pins that connect directly to the
EPXA10 device, supporting custom interfaces (see Table 59 on page 67)
PCI Interface
Two PCI slots, U9 and U10, are implemented on the EPXA10 DDR
development board. The 32-bit interface runs at up to 33 MHz and
operates at 3.3 V only; it complies with PCI Local Bus Specification, Revision
2.2. The slots must be used solely with 3.3 V and universal PCI cards.
1
Do not force a 5-V PCI card into a 3.3-V PCI connector; this could
damage the EPXA10 device.
User I/O pins are provided for the PCI interfaces. Table 52 on page 63
lists the PCI signal pin assignments.
14
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
EPXA10 Device Signal Definitions for PCI Cards
Table 4 lists the PCI signals for which EPXA10 device signals are required
to implement the PCI interface See Table 52 on page 63 for pin-out details..
Table 4. EPXA10 Device Signal Definitions for PCI Cards
Function
PCI Signal
Number
Address and data
AD[31..0]
C/BE[3..0]#
PAR
37
Interface control
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
LOCK#
6
Error reporting
PERR#
SERR#
2
Arbitration
PRSNT1#
PRSNT2#
REQ1#
REQ2#
GNT1#
GNT2#
6
Interrupts
INTA#
INTB#
INTC#
INTD#
4
System
CLK2
PCI_RST#
2
Some signals are not included in Table 4. IDSEL is a PCI signal used as a
device select for configuration cycles and is generally connected to one of
the address lines. Table 5 lists the IDSEL signal connections.
Table 5. IDSEL Signal Connections
Altera Corporation
Board Reference
PCI Slot
EPXA10 Board Reference
U10.A26
1
AJ19
U9.A26
2
AK19
15
EPXA10 DDR Development Board Hardware Reference Manual
Board-Level Issues
The PCI interface requires no devices on the board level if the PCI is
implemented as an IP core in the EPXA10 device. All of the power
supplies are provided when the ATX power supply is connected on the
EPXA10 DDR development board.
Table 6 lists the PCI interface characteristics.
Table 6. PCI Interface Characteristics
Interface Features
PCI Interface
I/O Pins
55 plus clock
Voltages
Clock Speed
+3.3 V, +5 V, ±12 V
33 MHz
10/100 Ethernet Parallel Interface
The Ethernet interface consists of a transceiver, or PHY layer, and
associated discrete components. You can use the interface to implement
an Ethernet media access controller (MAC) in the EPXA10 device. As
shown in Table 43 on page 53, the interface consists of standard mediaindependent interface (MII) and additional signals. Table 7 details the
devices used to implement the Ethernet interface.
Table 7. Ethernet Interface Device Reference
Board
Reference
Part Number
U8
78Q2120-64CGT (TQFP64)
TDK
www.tdk.com
U4
PE-68515L
Pulse
www.pulseeng.com 10/100-BASE T single-port
transformer module
P3
AMP 555078-1
AMP
www.amp.com
16
Manufacturer
Website Address
Description
Fast Ethernet MII transceiver
8-pin PCB RJ45 data socket
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Ethernet LEDs
Table 8 lists the LEDs used for the Ethernet on the EPXA10 DDR
development board.
Table 8. Ethernet LEDs
Board
Reference
Description
LEL
Link LED. This is set on during linkup
LEDTX
Transmit LED. This is set on during transmission
LEDRX
Receive LED. This is set on during receipt
LEDFDX
Full-duplex LED. This set on for full-duplex mode and off for halfduplex
LEDCOL
Collision LED. This is set on in half-duplex mode when a collision
occurs, and is held off in full-duplex mode
LEDBTX
100-BASE TX LED. This is set on for 100-BASE T connection, but
off otherwise
LEDBT
10-BASE T LED. This is set on for 10-BASE T connection, but is
off otherwise
Ethernet Switches
Table 9 lists the switches used for the Ethernet device in the DIPSW2 dipswitch bank; and Table 10 on page 18 lists the TECH switches, which are
used to set the Ethernet decoding protocol.
Table 9. DIPSW2 Switch Connections
Board Reference
Altera Corporation
Identifier
DIPSW2_1
ANEGA
DIPSW2_2
TECH0
DIPSW2_3
TECH1
DIPSW2_4
TECH2
DIPSW2_5
PHYAD0
DIPSW2_6
PHYAD1
DIPSW2_7
PHYAD2
DIPSW2_8
PHYAD3
DIPSW2_9
PHYAD4
Function
Auto-negotiation enable
Used to specify the Ethernet decoding
Physical Address
17
EPXA10 DDR Development Board Hardware Reference Manual
Table 10. Ethernet Protocol Decoding
TECH [2:0]
Function
0
0
0
No technology capability
1
1
1
Both 10-BASE T and 100-BASE T
0
0
1
10-BASE T, half duplex
0
1
0
100-BASE T, half duplex
0
1
1
Both 10-BASE T and 100-BASE T, half duplex
1
0
0
None
1
0
1
10-BASE T, full/half duplex
1
1
0
100-BASE T, full/half duplex
Serial I/O Interfaces
There can be two UARTs in the EPXA10 device. A dedicated UART is
located in the embedded stripe; optionally, an IP UART can be
implemented in the FPGA, connected to 3.3-V standard EPXA10 I/O pins.
Each UART is connected to a transceiver (U2 for the embedded stripe
UART and U3 for the IP UART) to convert LVTTL voltage for RS-232
compatibility at up to 256 Kbps. Each UART also has its own DB9 male
RS-232 connector wired as a DTE.
1
The transceiver uses a 3.3-V power supply. If the RS-232 input
pins are used as general-purpose outputs, contention occurs
because the bus transceiver is always active. If these pins are not
used as part of a design, ensure that they remain in the highimpedance state. All unused I/O pins can be set to tri-state mode
in the Quartus II software (see “Unused EPXA10 Device Pins” on
page 75).
Table 11 provides information on the devices used to implement the
RS-232 interface.
Table 11. RS-232 Interface Device Reference
Board
Part Number
Reference
Manufacturer
Website Address
Description
U2
MAX3241
Maxim
www.maxim-ic.com RS-232 DTE transceiver (connects to the
UART in the stripe using connector P1)
U3
MAX3241
Maxim
www.maxim-ic.com RS-232 DTE transceiver (connects to the soft
UART in the FPGA using connector P2)
See Table 42 on page 52 for information on the RS-232 signals.
18
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Table 12 gives the UART interface characteristics.
Table 12. DTE UART Interface Characteristics
Features
I/O Pins
Voltage (V)
UART 1 TX, RX & control
7
3.3
UART 2 TX, RX & control
7
3.3
Table 8 lists the UART LEDs on the EPXA10 DDR development board.
Table 13. UART LEDs
Board Reference
Signal
Description
TX_UART1
UART1_TXD This LED indicates activity on the line
RX_UART1
UART1_RXD This LED indicates activity on the line
TX_UART2
UART2_TXD This LED to indicates activity on the line
RX_UART2
UART2_RXD This LED indicates activity on the line
Memory Interfaces
The EPXA10 DDR development board supports the following types and
capacities of on-board memory, as listed in Table 14.
Table 14. Development Board Memory Characteristics
Type
Address
Lines
Data
Lines
Control
Lines
Memory Organization
DDR SDRAM
15
32
3
4 M × 32 × 4 banks
Flash
25
16
6
4 × 8 Mbytes
Size
128 Mbytes; 32-bit
32 Mbytes
DDR SDRAM
Four 256-Mbit DDR SDRAM chips are connected to the SDRAM
controller, giving a total of 128 Mbytes of 32-bit memory. Figure 3 on
page 20 shows how they are arranged.
Altera Corporation
19
EPXA10 DDR Development Board Hardware Reference Manual
Figure 3. DDR SDRAM Interface
Excalibur EPXA10
SD_CS0
Bank 0
SD_DQS0[3..0]
Bank 1
x1
SD_DQM0[3..0]
y2
y1
I/O[7..0]
I/O[15..8]
SD_DQ[7..0]
BA[1..0]
I/O[31..24]
SD_DQ[31..24]
SD_DQ[23..16]
BA[1..0]
Bank 3
x3
y3
I/O[23..16]
SD_DQ[15..8]
SD_DQ[31..0]
Bank 2
x2
BA[1..0]
BA[1..0]
SD_A[12..0]
SD_A[14..13]
Key
x1 SD_DQS1[3..0]
x2 SD_DQS2[3..0]
x3 SD_DQS3[3..0]
y1 SD_DQM1[3..0]
y2 SD_DQM2[3..0]
y3 SD_DQM3[3..0]
Table 15 provides information on the devices used to implement the DDR
SDRAM interfaces.
Table 15. DDR SDRAM Interface Device Reference
Board
Reference
Part Number
Manufacturer
Website Address
DDR1
MT46V32M8
Micron
www.micron.com
256 Mbit × 8-bit SDRAM
DDR2
MT46V32M8
Micron
www.micron.com
256 Mbit × 8-bit SDRAM
DDR3
MT46V32M8
Micron
www.micron.com
256 Mbit × 8-bit SDRAM
DDR4
MT46V32M8
Micron
www.micron.com
256 Mbit × 8-bit SDRAM
20
Description
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Table 16 shows the timing parameters that should be used when setting
up the EPXA10 SDRAM controller for use with Micron MT46V16M8 DDR
devices.
Table 16. Micron MT46V16M8 DDR Timing Parameters
Parameter
Value
Active to Read or Write (RCD)
20ns
Active to Precharge command (RAS)
45ns
Active bank A to Active bank B command (RRD)
15ns
Precharge command period (RP)
20ns
Write recovery time (WR)
15ns
Active to Active command period (RC)
65ns
Auto Refresh period (RFC)
65ns
Auto Refresh command interval (RFSH)
15625ns
CAS latency (CL)
2 – 2.5
Burst Length (BL)
8
Row address bits
12
Column address bits
10
Bank address bits
2
Flash Memory
Four 8-Mbyte flash memory chips are connected to the EBI of the EPXA10
device, giving a total of 32-Mbytes of 16-bit memory (see Figure 4).
Figure 4. Flash Memory Interface
Flash Memory (4 x 8 Mbyte)
1
EPXA10
A1-A21
2
3
4
A0-A20
D0-D15
EBI
OE, WE, CE
3.3 V
12 V
Programming
voltage
Altera Corporation
21
EPXA10 DDR Development Board Hardware Reference Manual
Table 17 provides information on the devices used to implement the flash
memory interfaces.
Table 17. Flash Memory Interface Device Reference
Reference
Part Number
Manufacturer
Website Address
FLASH1
28F640C3
Intel
www.Intel.com
256 Mbit × 16-bit flash memory
Description
FLASH2
28F640C3
Intel
www.Intel.com
256 Mbit × 16-bit flash memory
FLASH3
28F640C3
Intel
www.Intel.com
256 Mbit × 16-bit flash memory
FLASH4
28F640C3
Intel
www.Intel.com
256 Mbit × 16-bit flash memory
LED & Switch Interfaces
The EPXA10 DDR development board provides a variety of LED and
switch interfaces. Some are user-definable and some are function-specific.
Figure 5 on page 23 shows the location of LEDs and switches on the
development board.
22
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 5. Switches & LEDs on the EPXA10 DDR development Board
Application
LEDs. See
Table 19 on
page 24 for
details
Ethernet
switches.
See Table 9
on page 17
for details
Ethernet
LEDs. See
Table 19 on
page 24 for
details
Userdefined
switches.
See Table
18 on
page 24 for
details.
Application
LEDs. See
Table 19 on
page 24 for
details
Altera Corporation
User-defined LEDs.
See Table 20 on
page 25 for details.
User-defined pushbutton switches.
See Table 22 on
page 26 for details
Push-button switches.
See Table 21 on
page 26 for details.
23
EPXA10 DDR Development Board Hardware Reference Manual
User-Defined LEDs
On the EPXA10 DDR development board, there are eight user-definable
LEDs. They connect directly to the EPXA10 device I/O pins and can be
used for any kind of application.
Table 18 lists the user LEDs on the development board.
Table 18. LED Interface Characteristics
Feature
Board Reference
EPXA10 I/O Pin
Voltage (V)
USER_LED7
U26
T6
3.3
USER_LED6
U25
U7
3.3
USER_LED5
U24
V8
3.3
USER_LED4
U23
V7
3.3
USER_LED3
U22
U6
3.3
USER_LED2
U21
V5
3.3
USER_LED1
U20
U5
3.3
USER_LED0
U19
V6
3.3
Table 56 on page 65 provides more information on EPXA10 device pins
connected to LEDs.
Function-Specific LEDs
LEDs are also used for specific application functions, such as the
configuration, RS-232, and Ethernet interfaces. Table 19 lists the functionspecific LEDs, their power supply voltage, their connection details, and
their use.
Table 19. Function-Specific LED Usage (Part 1 of 2)
Signal
Board
Reference
EPXA10 I/O Pin (or
Board Connector)
Description
Voltage (V)
VCC_–5V
U27
–5-V power supply indicator
VCC_5V
U28
5-V power supply indicator
VCC_2.5V
U29
2.5-V power supply indicator
2.5
VCC_12V
U30
12-V power supply indicator
–12
VCC_3.3V
U31
3.3-V power supply indicator
3.3
VCC_–12V
U32
–12-V power supply indicator
–12
VCC_1.8V
U33
1.8-V power supply indicator
1.8
LED link signal indicator
3.3
LEDL
24
LEDL
(1)
–5
5
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Table 19. Function-Specific LED Usage (Part 2 of 2)
Signal
LEDTX
Board
Reference
EPXA10 I/O Pin (or
Board Connector)
Description
Voltage (V)
LEDTX
(1)
LED transmit signal indicator
3.3
LEDRX
(1)
LED receive signal indicator
3.3
LEDFDX
LEDFDX
(1)
LED full-duplex signal indicator
3.3
LEDCOL
LEDCOL
(1)
LED collision signal indicator
3.3
LEDBTX
LEDBTX
(1)
LED 100-BASE TX signal indicator
3.3
LEDRX
LEDBT
(1)
LED 10-BASE T signal indicator
3.3
UART1_TXD
TX_UART1
D28
Embedded stripe UART signal indicator
3.3
UART1_RXD
RX_UART1
D29
Embedded stripe UART signal indicator
3.3
LEDBT
UART2_TXD
TX_UART2
J29
FPGA UART signal indicator
3.3
UART2_RXD
RX_UART2
K29
FPGA UART signal indicator
3.3
INIT_DONE
INIT_DONE
D14
Used by FPGA initialization; signifies that
initialization is complete
3.3
Note
(1)
These pins are connected to the Ethernet transceiver and not directly to the EPXA10 device.
Switch Interfaces
In addition to the dip-switches used for the Ethernet interface, which are
listed in Table 9 on page 17, the EPXA10 DDR development board
provides nine user-definable switches in another dip-switch block, four
push-button switches, two dedicated reset switches and a switch to
generate an interrupt on the EBI controller. Table 20 documents the
interface characteristics of the dip-switch block, DIP_SW1.
Table 20. DIPSW1 Switch Connection
Board Reference
Altera Corporation
EPXA1 I/O Pin
Board Connector
Voltage (V)
DIPSW1.1
U8
U18.12
3.3
DIPSW1.2
T5
U18.13
3.3
DIPSW1.3
V4
U18.15
3.3
DIPSW1.4
V10
U18.16
3.3
DIPSW1.5
T7
U18.17
3.3
DIPSW1.6
W12
U18.19
3.3
DIPSW1.7
U9
U18.20
3.3
DIPSW1.8
V11
U18.21
3.3
DIPSW1.9
R6
U18.23
3.3
25
EPXA10 DDR Development Board Hardware Reference Manual
The push-button switches and integrated LEDs are connected to the
EPXA10 I/O pins. Tables 21 and 22 detail the push-button switches.
Table 21. Push-Button Switches
Board Reference
SW_RESET
SW_DEV_CLR_N
SW4 INT
EPXA10
I/O Pin
Signal
Use
Voltage
(V)
R30
NCONFIG
Generates a warm reset
3.3
H3
GLOBNRS
Resets the FPGA
3.3
G25
int_extpin_n Generates an interrupt on the EBI interface when
enabled by the interrupt controller; also connected to
user-defined I/O
3.3
Table 22. User-Definable Push-Button Switches
Board Reference
EPXA10 I/O
Pins
Board
Connector
Signal
Voltage
(V)
SW1
T8
U18.24
USER_PB0
3.3
SW2
R5
U18.25
USER_PB1
3.3
SW3
U4
U18.27
USER_PB2
3.3
SW4
U10
U18.28
3.3
SW4 INT
G25
USER_PB3
also
int_extpin_n
3.3
Trace Port Interface
A matched-impedance connector (MICTOR) is connected to the ETM9 trace
module. It is used in conjunction with trace tools such as ARM Trace and
Lauterbach to debug the software in real time. ETM9 trace tools are
connected to PROC_JTAG signals. Table 23 gives details of the device used.
Table 23. Interface Device Reference
Board
Reference
TRACE PORT
Part Number
Manufacturer
AMP ref 2-767004-2
AMP
Website
Address
http:/www.amp.com
Description
Connected to the ETM9
10-Pin IDC Header Interface
The 10-pin header interface, HEADER1, facilitates connection to pins on
the expansion header, which in turn connect to the user I/O on the
EPXA10 device. The pins on the header are arranged in a 5 × 2 matrix.
26
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Expansion Header Interface
The EPXA10 DDR development board hosts the EPXA10 device and four
expansion headers, which are implemented on the board for use with
daughter cards. The expansion headers are implemented using Samtec
TOLC 200-pin connectors, as listed in Table 24 on page 27. They are
connected to I/O pins on the EPXA10 device. Headers U16, U17, and U18
include +5-V, +3.3-V, ±12-V, and ground signals, as well as I/O signals.
Header U15 only has I/O signals and clock signals.
Table 24 on page 27 provides information on the devices used to
implement the expansion header interface.
Table 24. Expansion Header Interface Device Reference
Board
Reference
Part Number
Manufacturer
Website Address
Description
U15
SAMTEC
TOLC-150-32-F-Q
Samtec
www.samtec.com
Connector to expansion card
U16
SAMTEC
TOLC-150-32-F-Q
Samtec
www.samtec.com
Connector to expansion card
U17
SAMTEC
TOLC-150-32-F-Q
Samtec
www.samtec.com
Connector to expansion card
U18
SAMTEC
TOLC-150-32-F-Q
Samtec
www.samtec.com
Connector to expansion card
Note:
(1)
Altera recommends that you use Samtec SOLC-150-02-F-Q for the daughter board connectors.
Table 25 lists the expansion header interface characteristics.
Table 25. Expansion Header Interface Characteristics
Interface
Expansion header
I/O Pins Signalling
Voltage (V)
501
±3.3
Clock
Voltages (V)
33 MHz
+3.3, +5, ±12
All USER LEDs, switches, push buttons, and the 10-pin IDC connector are
accessible from the expansion headers.
The expansion headers can be used to interface to special-function
daughter cards; contact your Altera representative for details of the
daughter cards available. By using the I/O pins on the EPXA10 device and
power supplies from the EPXA10 DDR development board, you can
design expansion cards to your specific requirements.
Altera Corporation
27
EPXA10 DDR Development Board Hardware Reference Manual
The connectors are stackable, so more than one card can be plugged on
each header, allowing you to develop different cards for individual
modules within a complex design.
1
Refer to Figures 6 to 9 for mechanical drawings of the board
expansion headers and Tables 56 through 59 for EPXA10 pin
details and their connections on the expansion headers.
Figure 6 on page 28 shows the location of the expansion headers on the
EPXA10 DDR development board.
Figure 6. EPXA10 DDR development Board TOLC Expansion Header
Connections
U16
U15
EPXA10
U18
U17
28
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
The dimensions given in Figures 7 to 9 are inches, measured from the
centre of the pad.
Figure 7 gives dimensions for the TOLC expansion headers categorized in
Table 24 on page 27.
1.9500
Figure 7. EPXA10 DDR development Board TOLC Dimensions
2.7250
3.8000
0.8700
0.6830
1
All dimensions are in inches.
To connect to the motherboard, a daughter board must use SOLC
connectors, for which dimensions are given in Figure 8 on page 30.
Altera Corporation
29
EPXA10 DDR Development Board Hardware Reference Manual
Figure 8. Daughter Board SOLC Dimensions
1.9400
2.7250
3.8000
0.8570
0.6690
a
1
All dimensions are in inches.
Figure 9 on page 31 is a mechanical diagram giving the position of the
TOLC connectors on the motherboard layout.
1
30
The PCB footprints for TOLC and SOLC connectors differ.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 9. Mechanical Diagram of the EPXA10 DDR development Board Expansion Headers
X
DIA. 0.132" x 4 off
X
Centre of
U15 pin 1
PCB pad
X
2.100
2.800
2.300
2.075
O
O
Centre of
U16 pin 1
PCB pad
0.125
X
0, 0
0
X
XA1 center
O
1.725
O
2.800
X
2.600
2.250
X
Centre of
U18 pin 1
PCB pad
X
Centre of
U17 pin 1
PCB pad
0.900
1.400
1.600
1.250
1.370
2.050
2.200
1
Altera Corporation
All dimensions are in inches.
31
EPXA10 DDR Development Board Hardware Reference Manual
To design a matching daughter board, designers must do one of the
following:
■
■
Jumper
Configuration
Base designs on the SOLC expansion header dimensions given in
Figure 8 on page 30
Translate dimensions from the TOLC motherboard dimensions
The jumpers on the EPXA10 DDR development board serve several
functions:
■
■
■
■
■
■
■
Clock distribution
Enabling clocks
Selecting clocks
JTAG configuration
Enabling the PLL interface
Selecting VPP voltage
Driving logic signals to the MAX 3032 device
Figure 10 on page 33 shows the location of the jumpers on the
development board.
32
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 10. Jumper Locations
JP8
JP7
JP3
JP_VPP
JP2
JP1
JP6
JP5
JP4
MSEL0
MSEL1
JSELECT
BOOT_FLASH
DEBUG_EN
JF2
JF1
JP9
JP10
JP_AGND2GND
Altera Corporation
33
EPXA10 DDR Development Board Hardware Reference Manual
Table 26 lists the jumpers on the EPXA10 DDR development board.
Table 26. Jumpers on the EPXA10 DDR development Board
Jumper &
Description
EPXA10 I/O Pin
(Board Connection)
Pins 1-2 Connected
Pins 2-3 Connected
Default
JP1 (7)
X1 Osc Disabled
X1 Osc Enabled
2-3
JP2 (7)
X2 Osc Disabled
X2 Osc Enabled
2-3
JP3 (5)
CLK1=Ext_Osc0
CLK1=TX_CLK
1-2
JP4 (7)
X4 Osc Disabled
X4 Osc Enabled
2-3
JP5 (7)
X5 Osc Disabled
X5 Osc Enabled
2-3
JP6 (7)
X6 Osc Disabled
X6 Osc Enabled
2-3
JP7 (6)
PHY 25MHz Clock Disabled PHY 25MHz Clock Enabled
2-3
JP8 (5)
CLK2=Ext_Osc1
1-2
CLK2=RX_CLK
JP9 (2)
Y30
(U13.87)
CLK3->LVDSTXINCLK1p
-
None
JP10 (2)
W30
nCLK3->LVDSTXINCLK1n
-
None
JF1(8)
JF2(8)
MAX3032.2
MAX3032.3
MAX3032.5
-
MSEL0 (1)
J30
MSEL0=0
MSEL=1
1-2
MSEL1 (1)
K30
MSEL1=0
MSEL1=1
1-2
JSELECT (3)
C24
JSELECT=0
JSELECT=1
1-2
DEBUG_EN (4)
B10
DEBUG_EN=0
DEBUG_EN=1
2-3
BOOT_FLASH (1)
C10
BOOT_FLASH=0
BOOT_FLASH=1
2-3
JP_VPP
VPP=12 V
VPP=3.3 V
2-3
JP_AGND2GND
Analog to digital GND
-
1-2
Note:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
34
Used to select configuration mode. See “Configuration Schemes” on page 44.
Connects clock 3 for LVDS. See AN 115: Using the ClockLock and ClockBoost PLL Features in APEX Devices.
Determines whether serial or dual JTAG chains are used for debugging.
Enables/disables debugging.
Connects clocks 1 or 2 to the Ethernet clock.
Enables/disables the Ethernet clock.
Enables/disables clocks.
JF1 and JF2 used in combination to drive a signal to specific pins on the MAX 3032 device.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Jumpers JF1 and JF2 are used to drive logic values to the MAX 3032 device.
When corresponding pins on JF1 and JF2 are connected, logic 1 is driven
to a pin on the MAX 3032; when they are not connected, logic 0 is driven.
Table 27 on page 35 demonstrates this and indicates which pin on the
MAX 3032 device is connected to the jumper pins.
Table 27. JF1 & JF2 Connections
Clocks
JF1 & JF2 Pin
Signal when
Connected
Signal when
Disconnected
MAX 3032 Pin
1
Logic 1
Logic 0
5
2
Logic 1
Logic 0
3
3
Logic 1
Logic 0
2
The clocks on the EPXA10 DDR development board can be enabled and
disabled according to your design requirements. They supply the clocks
for the EPXA10 device’s embedded stripe and FPGA, and also for the onboard peripherals. The Ethernet clock is a dedicated on-board 25-MHz
crystal oscillator. The remaining clocks can be selected from the following
clock sources:
■
■
■
On-board crystal oscillator (12 MHz, 25 MHz, 32 MHz, 48 MHz,
depending on the clock)
Alternative crystal oscillator, plugged into the appropriate DIL14
socket, depending on the clock
Waveform generator, using the appropriate BNC connector,
depending on the clock
1
If you plug in an alternative crystal oscillator for a clock, it drives
the same clock line as the BNC connector. To drive a clock
through the BNC connector, you must remove the alternative
crystal oscillator (if one is connected) and disable the associated
on-board crystal oscillator.
CLK1 and CLK2 inputs can either be connected to the RX and TX ethernet
clocks or to CLK1 or CLK2 on the board using jumpers 3 and 8. Refer to
“Jumper Configuration for the Clock Input” on page 40 for more about
configuring the clock options on the development board.
Table 28 on page 36 lists the development board clocks and their
selectable sources, and Figure 11 on page 37 shows their location on the
EPXA10 DDR development board.
Altera Corporation
35
EPXA10 DDR Development Board Hardware Reference Manual
Table 28. Clocks Note (1)
Board
Reference
EPXA10
Reference
Selectable Board
Source
EPXA10 I/O Pin
(Board Connection)
Used In
Speed
(MHz)
STRIPE_CLK
CLK_REF
BNCJ5/X5/U11
A28
EPXA10 stripe
50
CLK1_IN
CLK1
BNCJ1/X1/U6
N30
FPGA
12
CLK2_IN
CLK2
BNCJ2/X2/U5
Y3
FPGA
25
PCI_CLK_IN
CLK3
BNCJ6/X6/U7
W30
(U9.B16, U10.B16)
FPGA; PCI
32
CLK4_IN
CLK4
BNCJ4/X4/U12
P3
FPGA
48
Ethernet
25
CKIN
(U8.4)
Note:
(1)
36
See “Sources for the EPXA10 Clocks” on page 40 for details of selecting a source for the EPXA10 clocks.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 11. Clock Generators on the EPXA10 DDR development Board
CLK_REF & the FPGA Clocks
The reference clock for the EPXA10 embedded stripe (CLK_REF) uses a
zero-delay clock buffer to allow a 3.3-V to 5-V interface as well as
buffering the clock signal.
The four FPGA clocks service the ClockLock™ and ClockBoost™ circuitry
on the Excalibur device. They go through a MAX 3032 device to give 5-V
compatibility and to act as a buffer.
Altera Corporation
37
EPXA10 DDR Development Board Hardware Reference Manual
MAX 3032
The Altera MAX 3032 is a PLD that is used in this design as an economic
method of delivering maximum flexibility for the clock distribution on the
EPXA10 DDR development board. It allows you to use 5-V clock input
signals using DIL14 sockets or SMA connectors. Control signals have been
added to the PLD to give some extra flexibility if, for example, the clock
input signal needs to be sequenced or stopped.
On the EPXA10 DDR development board, the MAX 3032 is programmed
using minimal logic—all clocks use straight connections from input to
output, as does the reset signal. The only logic used in the MAX 3032 is a
tri-state buffer to held NSTATUS and prevent any power-up sequencing
problem.
Figure 12 shows the connections on the MAX 3032 device.
Figure 12. Block Diagram Showing MAX 3032 Connections
CLK1_IN
CLK1
CLK2_IN
CLK2
PCI_CLK_IN
PCI_CLK
CLK4_IN
CLK4
NRESET
MAX 3032
IO2MAX
GLOBNRS_IN
GLOBNRS
INIT_DONE
IO1
CONF_DONE
IO2
IO_CLKUSR
IO3
Embedded Stripe Clocks
Table 29 on page 39 lists the clocks on the EPXA10 device and their
sources on the development board.
The clocks on the development board can be configured as required,
depending on which devices are used.
38
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Table 29. EPXA10 DDR development Board Clock Sources
EPXA10 Pin
Name
EPXA10 Pin
Number
Board
Connection
Description
Test Point
CLK_REF
A28
STRIPE_CLK
50-MHz main clock provided to the
synchronous memory and embedded
processor. Dedicated input
TP_CLK_REF
CLK1
N30
CLK1_IN
MAX3032.25
JP3
12-MHz clock input
TP_CLK1
CLK2
Y3
CLK2_IN
MAX3032.28
JP8
25-MHz clock input
TP_CLK2
CLK3
W30
JP9
PCI_CLK_IN
32-MHz clock input
TP_CLK3
CLK4
P3
CLK4_IN
MAX3032.22
48-MHz clock input
TP_CLK4
IO/CLK1A
V30
NCLK1
Clock input in LVDS mode
TP_NCLK1
IO/CLK2A
R3
NCLK2
Clock input in LVDS mode
TP_NCLK2
IO/CLK3A
Y30
NCLK3
Clock input in LVDS mode
TP_NCLK3
IO/CLK4A
N3
NCLK4
Clock input in LVDS mode
TP_NCLK4
IO/CLKFBIN1A
AM28
NCLK1_FB
Dedicated pin that allows external feedback to TP_NCLK1_FB
the PLL in LVDS mode
IO/CLKFBIN2A
J3
NCLK2_FB
Dedicated pin that allows external feedback to TP_NCLK2_FB
the PLL in LVDS mode
IO/LOCKOUT0
AC30
IO/LOCKOUT1
IO/LOCKOUT2
IO/LOCKOUT3
PLLENABL
CLKOUT0
AM29
CLK1_OUT
Dedicated pin that allows the PLL output to be TP_CLK1_OUT
driven off-chip
CLKOUT1
AH3
CLK2_OUT
Dedicated pin that allows the PLL output to be TP_CLK2_OUT
driven off-chip
CLKFBIN0
AL28
CLK1_FBp
Dedicated pin that allows external feedback to TP_CLK1_FBp
the PLL
CLKFBIN1
K3
CLK2_FBp
Dedicated pin that allows external feedback to TP_CLK2_FBp
the PLL
Altera Corporation
U16.83
Status of ClockLock PLL1
AK4
U16.8
Status of ClockLock PLL2
H30
U16.85
Status of ClockLock PLL3
AK5
U16.3
Status of ClockLock PLL4
P30
U16.83
Dedicated pin used for PLL circuitry
39
EPXA10 DDR Development Board Hardware Reference Manual
Jumper Configuration for the Clock Input
Jumpers JP1 to JP10 are used to select different clock inputs:.
■
■
■
■
■
JP1, JP2, and JP4 to JP6 enable and disable the clocks (X1, X2, and X4
to X6, respectively)
JP3 is used to set CLK1 to oscillator 0 (position 1-2) or to the Ethernet
clock, TX_CLK (position 2-3)
JP7 enables and disables the Ethernet clock
JP8 is used to set CLK2 to oscillator 1 (position 1-2) or to the Ethernet
clock, RX_CLK (position 2-3)
JP9 and JP10 can be used to connect CLK3 to lvdstxinclk1p and
NCLK3 to lvdstxclk1n, respectively
During development, if you need to run any of the clocks at a slower or
faster rate, you can do so using either the external clock input or a variable
oscillator.
Sources for the EPXA10 Clocks
There are three options for providing a source for the EPXA10 stripe
clocks:
■
■
■
External clock generator
Main clock
An alternative crystal oscillator
Using an External Clock Generator
To select the external clock generator for a clock input, set the appropriate
jumper to position 1-2 to disable the main clock.
Using the Main Clock
To use the main clock for a clock input, set the appropriate jumper to
position 2-3 to enable the crystal oscillator.
Using a Variable Oscillator
To use a variable oscillator as a clock input, follow the steps below:
40
1.
Plug in the DIL14 crystal oscillator package to the appropriate
socket.
2.
Disable the relevant main clock, by connecting pins 1 and 2 of the
appropriate jumper (see Table 26 on page 34).
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
3.
Provide a 5-V power supply on the board, either by connecting the
ATX power supply or by connecting an alternative 5-V input to JP11.
1
Device
Configuration
The clock buffer and the MAX 3032 are 5-V compatible; they
convert 5-V input from the crystal oscillator to the 3.3 V required
for the clocks’ inputs.
There are three methods of configuring and programming the EPXA10
device:
■
■
■
Booting from flash memory
Configuring the device from the EPC16
Using the Quartus® II software to configure the device using the
JTAG interface
1
On the EPXA10 device, the settings of BOOT_FLASH, MSEL0, and
MSEL1 determine the configuration mode and method. See
Figure 10 on page 33 for their location on the EPXA10 DDR
development board.
See “JTAG Interfaces” on page 45 for more details about using a JTAG
interface.
Booting from Flash Memory
The Altera flash memory programmer (exc_flash_programmer.exe) is a
utility that allows you to program flash memory on the EBI using the
JTAG interface and the ByteBlasterMV or MasterBlaster download cable.
After reset, the processor boots up and executes the bootloader from flash
memory. The bootloader configures the stripe, loads the user software
into memory, configures the FPGA side of the EPXA10, and then begins
to execute the user code.
Table 30 summarizes the board jumper requirements for booting from
flash memory.
Table 30. Jumper Settings for Booting from Flash Memory
f
Altera Corporation
BOOT_FLASH
MSEL0
MSEL1
Mode
1
0
0
Boot from 16-bit flash
For further details about booting the device from flash memory, refer to
the Excalibur Devices Hardware Reference Manual.
41
EPXA10 DDR Development Board Hardware Reference Manual
Configuring Using the EPC16
The Quartus II software can generate a programmer object file (.pof)
containing both hardware and software, for downloading into the EPC16
device on the EPXA10 DDR development board. For more details, see
“EPC16 Configuration Device” on page 44.
1
The EPC16 device can be programmed with the Quartus II
software version 1.1 or higher, using either the MasterBlaster or
ByteBlasterMV download cables.
Table 31 summarizes the jumper requirements for booting your system
from an EPC16.
Table 31. Jumper Settings for Booting from a Serial Device
BOOT_FLASH
MSEL0
MSEL1
Mode
0
0
0
Serial
When power is applied to the development board, the EPC16
configuration device loads configuration data into the EPXA10 device, if
it has been programmed. If you change the configuration device’s
programming information, you must turn the board off and on before
new information can be loaded into the EPXA10 device.
The EPC16 device can be programmed through the JTAG interface; see
“EPC16 Configuration Device” on page 44.
To configure the device using the EPC16 device, start the Quartus II
software, and specify the EPC16 as an output option to create the required
.pof files. If the EPC16 is not specified, the Quartus II software generates
a single file to program the EPXA10 device directly.
When configuring an Excalibur device using the EPC16 configuration
device, some simple logic must be placed in the system to allow both the
Excalibur and EPC16 devices to fully come out of reset before any
configuration begins.
During a configuration, the EPC16 uses the signals OE (connected to
nSTATUS on the Excalibur device) and nCS (connected to CONF_DONE on
the Excalibur device) to determine what action it should take.
42
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
In its long power-on-reset (POR) mode, the EPC16 begins sampling
CONF_DONE and OE approximately 100 ms after power-up. If the
Excalibur device is still in POR after this 100 ms, the signals from the
Excalibur device that control the state of the EPC16 could be in an
unknown state when the EPC16 begins sampling them, which results in
indeterminate behavior. Therefore, you must provide logic to hold these
signals low until the Excalibur device’s nRESET signal is deasserted. By
holding nSTATUS and OE low, the reset of the EPC16 can be extended
until the Excalibur device has also come out of POR. By holding
CONF_DONE and nCS low, the EPC16 does not erroneously sample it as
being high, which falsely indicates that the Excalibur device has already
been configured. Because both signals are open-drain, they can safely be
driven low by external logic without causing contention. Once nRESET
goes high, the Excalibur device is ready and the signals can be tri-stated
by the external logic to operate normally. As opposed to nPOR, nRESET
deasserts some time after the Excalibur device comes out of POR. For this
reason use the nRESET signal, not NPOR, to control the tri-stating of
nSTATUS and CONF_DONE, to provide a margin of safety. Figure 13
shows the circuit that accomplishes the reset dependency requirements.
Figure 13. Reset Dependency Circuit
nRESET
nSTATUS and OE
CONF_DONE and nCS
Configuring Using JTAG
The Quartus II software can generate an SRAM object file (.sof) containing
both hardware and software.
The Quartus II programmer uses the .sof file to configure the EPXA10
device via JTAG, using either the MasterBlaster or ByteBlasterMV
download cables. For more details, see “MasterBlaster/ByteBlasterMV
Communications Cable” on page 44.
For further details of how to create a .sof file and configure the EPXA10
device via JTAG, consult the Quartus II Help.
Table 32 summarizes the jumper requirements for booting your system
from an EPC16.
Altera Corporation
43
EPXA10 DDR Development Board Hardware Reference Manual
Table 32. Jumper Settings for Configuring Using JTAG
BOOT_FLASH
MSEL0
MSEL1
Mode
1
0
0
Serial
Configuration Schemes
Table 33 lists the serial configuration schemes that are available for the
EPXA10 device.
Table 33. Supported Serial Configuration Schemes
Configuration Scheme
Data Source
Configuration device
EPC16 configuration device
JTAG
MasterBlaster/ByteBlasterMV download cable
EPC16 Configuration Device
The EPC16 is part of the on-board JTAG chain that allows in-system
programming. The device is an EPC16 88-pin Ultra FineLine BGA; it
contains reprogrammable flash memory to use for serial device
configuration. For more details about configuring these devices, refer to
the data sheet Configuration Devices for ACEX, APEX, FLEX & Mercury
Devices.
f
For signal details of the EPC16 device, refer to the EPC16 pin-out table.
MasterBlaster/ByteBlasterMV Communications Cable
The ByteBlasterMV and MasterBlaster cables have a 10-pin header for use
with the development board. The cable allows you to download hardware
and software configuration data directly to the EPXA10 device or to the
EPC16 configuration device. The development board supports only JTAG
download mode, not passive serial download mode. The MasterBlaster
and ByteBlasterMV cables also support in-circuit hardware debugging
with the SignalTap® embedded logic analyzer.
1
Debugging
Features
44
The MasterBlaster cable can also be used in conjunction with the
ARM debugger to debug your software using JTAG.
On the EPXA10 DDR development board, a variety of debugging tools,
both Altera and third-party products, can be used in conjunction with the
JTAG interfaces to debug systems under development.
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Third-Party Debugging Tools
Third-party debugging tools such as Lauterbach and the GNUPro XRAY
debugger can be used with the EPXA10 DDR development board. For
latest details of which tools are available, access the Altera website at
http:/www.Altera.com.
JTAG Interfaces
There are three JTAG interfaces on the EPXA10 DDR development board:
■
■
■
The MB_BLASTER connector is used to connect an Altera ByteBlaster
or MasterBlaster download cable
The MULTI_ICE connector is used to connect a Multi-ICE cable or
any other compatible cable
The TRACE_PORT connector is used to connect a trace capture unit
or logic analyzer
The MB_BLASTER connector can be used with both the flash programmer
and the Quartus programmer, using the ByteBlasterMV and
MasterBlaster cables; and can be used to program the EPC16. The
MasterBlaster and ByteBlasterMV cables also support in-circuit hardware
debugging on the MB_BLASTER connector, using the SignalTap®
embedded logic analyzer. The JSELECT setting does not affect these
functions.
Using JSELECT
The JSELECT jumper determines whether a JTAG debugger can be
connected to the MB_BLASTER connector, the MULTI_ICE connector, or
the TRACE_PORT connector. shows the JSELECT settings required.
Table 34. Using JSELECT to Select a Debugging Connector
Debugger
Altera Corporation
JSELECT Value
Altera-RDI via a ByteBlasterMV or MasterBlaster cable
‘1’
Multi-ICE or a compatible device on the Multi-ICE connector
‘0’
Trace port connector or a compatible device on the trace port
connector
‘0’
45
EPXA10 DDR Development Board Hardware Reference Manual
1
Damage can result if you simultaneously connect a device that
drives the JTAG pins on the trace port connector and another
device on the Multi-ICE connector.
You can simultaneously connect one device to the MB_BLASTER
connector and another to one of the other two connectors; or you
can connect devices to the trace port and Multi_ICE connectors
at the same time, providing that the device on the trace port
connector does not drive the JTAG pins on that connector.
Using MasterBlaster/ByteBlasterMV Cable to Program the EPC16 Device
The EPC16 device can be programmed using the Quartus II software,
version 1.1, or higher, using either the MasterBlaster or ByteBlasterMV
download cable.
Figure 14 on page 47 shows how the MasterBlaster, ByteBlasterMV, and
Multi-ICE cables are connected.
46
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Figure 14. Connecting the MasterBlaster, ByteBlasterMV or Multi-ICE Cables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
VCC
PROC_NTRST
GND
PROC_TDI
GND
PROC_TMS
GND
PROC_TCK
GND
GND
GND
PROC_TDO
GND
NSRST
GND
NC
GND
NC
GND
2
4
6
8
10 12 14 16 18 20
9
7
5
3
1
1
3
5
7
9
11 13 15 17 19
10
8
6
4
2
Multi_ICE
1
2
3
4
5
6
7
8
9
10
TCK
GND
TDO
VCC
TMS
VIO
TCK
NC
TDI
GND
M/B Blaster
EPXA10
Device
JSELECT
Development Board
Power Supply
The EPXA10 DDR development board can be powered by either a
laboratory bench power supply or a commercially-available, PC-style
power supply (ATX). The bench supply provides 3.3-V; the ATX supply
provides voltage levels of ±12 V, ±5 V, and +3.3 V. The development
board derives VTT (1.25-V), VREF (1.25-V), +2.5-V, and +1.8-V supplies
from the input power supply. If there are no devices attached to the PCI
connectors, only the 3.3-V supply input is necessary, but to use devices on
the PCI connectors, you need an ATX power supply to provide the
different voltages.
1
Ensure that the voltage setting on the ATX power supply is set to
the appropriate voltage, based on the AC power outlet supply.
Figure 15 on page 48 shows the location of the power supply inputs for
the EPXA10 DDR development board.
Altera Corporation
47
EPXA10 DDR Development Board Hardware Reference Manual
Figure 15. EPXA10 Power Supply Inputs
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
5V
5V
-5 V
GND
GND
GND
main switch
GND
-12 V
3.3 V
12 V
NC
PWR_OK
GND
5V
GND
5V
GND
3.3 V
3.3 V
10
20
1
11
NC
GND
GND
5V
3.3 V
1
See Figure 1 on page 11 to see the development board layout in
greater detail.
A status LED is provided for each power supply source; see Table 19 on
page 24.
48
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
1
The total current that can be drawn depends on the daughter
card power supply, as follows: 1 A for 3.3 V, 5 V, or 12 V; and
100 mA for –12 V. This can be drawn from a single pin, but
designers should use as many of pins available on the header as
possible, to ease the power distribution on the daughter card.
Tables 35 through 40 list the estimated power requirements for the
development board.
Table 35. ±12.0-V Supply Requirements
Module
PCIs
mA (12 V)
500
mA (–12 V)
100
Table 36. 5.0-V Supply Requirements
Module
PCI
mA (5 V)
Depends on system
Alternative crystal oscillator
CLK_REF
CLK1
5
CLK2
5
CLK3
5
CLK4
5
ATX PSU
1000 (to provide adequate regulation)
Table 37. 3.3-V Supply Requirements
Module
EPXA10 I/O
Flash memory
PCIs
UARTs
Ethernet
LEDs
EPC16
Crystal oscillator
Power-on reset
Clock buffers
Altera Corporation
mA (3.3 V)
Depends on application
300
7.6A (system-dependent)
50
20 × 22
50
15 × 5
10
32 × 2
49
EPXA10 DDR Development Board Hardware Reference Manual
Table 38. 2.5-V Supply Requirements
Module
DDR SDRAM
mA (2.5 V)
500 mA
Table 39. 1.8-V Supply Requirements
Module
EPXA10 device core
mA (1.8 V)
Depends on application
Table 40. 1.25-V Supply Requirements
Module
VTT
VREF
50
mA (1.25 V)
1500
25
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Test Points
Table 41 on page 51 lists the test points on the EPXA10 DDR development
board.
Table 41. EPXA10 DDR development Board Test Points
Test Point
Connected To
Test Point
Connected To
GND1
GND
TP_NCLK1_FB
NCLK1_FB
GND2
GND
TP_NCLK2_FB
NCLK2_FB
GND3
GND
TP_CS0_N
CS0_N
GND4
GND
TP_CS1_N
CS1_N
GND5
GND
TP_CS2_N
CS2_N
GND6
GND
TP_CS3_N
CS3_N
GND7
GND
TP_EBI_CLK
EBI_CLK
TP_CLK_REF
CLK_REF
TP_OE_N
OE_N
TP_CLK1
CLK1
TP_WE_N
WE_N
TP_CLK2
CLK2
TP_TCK
TCK
TP_CLK3
CLK3
TP_TDI
TDI1
TP_CLK4
CLK4
TP_TDO
TDO1
TP_CLK1_FBP
CLK1_FBP
TP_TMS
TMS1
TP_CLK1_OUT
CLK1_OUT
TP_CLK2_FBP
CLK2_FBP
–12V
–5V
Test points for input power
supply
TP_CLK2_OUT
CLK2_OUT
1.8V
TP_NCLK1
NCLK1
12V
TP_NCLK2
NCLK2
2.5V
TP_NCLK3
NCLK3
3.3V
TP_NCLK4
NCLK4
5V
U34
Altera Corporation
ATX POWER_OK
51
EPXA10 DDR Development Board Hardware Reference Manual
Signals
Tables 42 through 46 document the signals for the following peripherals:
■
■
■
■
UART
PCI card
Trace port
Configuration/debugging interfaces
UART
Figure 16 shows the UART DB9 male connector used on the development
board.
Figure 16. DTE UART DB9 Male Connector
1
2
6
4
3
7
8
5
9
Table 42 lists the UART DB9 signals.
Table 42. DTE UART DB9 Male Connector Signals Note (1)
Pin
Signal
Description
1
DCD
Data carrier detect
2
RXD
Receive data
3
TXD
Transmit data
4
DTR
Data terminal ready
5
GND
Signal ground
6
DSR
Data set ready
7
RTS
Request to send
8
CTS
Clear to send
9
RI
Ring indicator
Note:
(1)
The EPXA10 DDR development board has two DB9 male connectors.
See Table 53 on page 64 for UART pin-out information.
52
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
PCI
Table 43 lists the PCI connector signals used on the development board.
Table 43. PCI Card 3.3-V-Only Connector
Pin
Signal
Pin
Signal
Pin
Signal
Pin
SIgnal
A1
TRST#
A2
+12 V
B1
–12 V
B2
TCK
A3
TMS
A4
TDI
B3
GND
B4
TDO
A5
+5 V
A6
INTA#
B5
+5 V
B6
+5 V
A7
INTC#
A8
+5 V
B7
INTB#
B8
INTD#
A9
RESERVED
A10
V I/O
B9
PRSNT1#
B10
RESERVED
A11
RESERVED
A12
RESERVED
B11 PRSNT2#
B12
RESERVED
A13
RESERVED
A14
3.3 V AUX
B13 RESERVED
B14
RESERVED
A15
RST#
A16
V I/O
B15 GND
B16
PCI_CLK
A17
V I/O
A18
GNT1#
B17 GND
B18
REQ1#
A19
GND
A20
AD [30]
B19 V I/O
B20
AD [31]
A21
+ 3.3 V
A22
AD [28]
B21 AD [29]
B22
GND
A23
AD [26]
A24
GND
B23 AD [27]
B24
AD [25]
A25
AD[24]
A26
IDSEL
B25 VCC
B26
C/BE3#
A27
+ 3.3 V
A28
AD[22]
B27 AD[23]
B28
GND
A29
AD[20]
A30
GND
B29 AD[21]
B30
AD[19]
A31
AD[18]
A32
AD[16]
B31 VCC
B32
AD[17]
A33
+ 3.3 V
A34
FRAME#
B33 C/BE2#
B34
GND
A35
GND
A36
TRDY#
B35 IRDY#
B36
+ 3.3 V
A37
GND
A38
STOP#
B37 DEVSEL#
B38
GND
A39
+ 3.3 V
A40
RESERVED
B39 LOCK#
B40
PERR#
A41
RESERVED
A42
GND
B41 + 3.3 V
B42
SERR#
A43
PAR
A44
AD[15]
B43 + 3.3 V
B44
C/BE1#
A45
+ 3.3 V
A46
AD[13]
B45 AD[14]
B46
GND
A47
AD[11]
A48
GND
B47 AD[12]
B48
AD[10]
A49
AD[9]
A50
GND
B49 M66EN
B50
GND
A51
GND
A52
C/BE0#
B51 GND
B52
AD[8]
A53
+ 3.3 V
A54
AD[6]
B53 AD[7]
B54
+ 3.3 V
A55
AD[4]
A56
GND
B55 AD[5]
B56
AD[3]
A57
AD[2]
A58
AD[0]
B57 GND
B58
AD[1]
A59
V I/O
A60
REQ64#
B59 + 3.3 V
B60
ACK64#
A61
+5V
A62
+5V
B61 + 5 V
B62
+5V
See Table 52 on page 63 for pin-out information for the PCI connectors.
Altera Corporation
53
EPXA10 DDR Development Board Hardware Reference Manual
Trace Port
Table 44 lists the ETM9 trace port signals.
Table 44. Trace Port Signals
Pin
Signal
Description
Pin
Signal
Description
1 NC
No connection
2 NC
No connection
3 NC
No connection
4 NC
No connection
5 GND
Ground
6 TRACECLK
Clock output for the trace port
7 DBGRQ
Not used
8 DBGACK
Output (not used)
9 nSRST
System reset detector
10 EXTTRIG
Output (not used)
11 TDO
Test data input
12 VTRef
Reference voltage input
13 RTCK
Input (not used)
14 VSupply
Power input for the debug equipment
15 TCK
Test clock output
16 TRACEPKT7
17 TMS
Test mode select output
18 TRACEPKT6
Data/address information output on
pipeline status
19 TDI
Test data output
20 TRACEPKT5
21 nTRST
Reset input/output
22 TRACEPKT4
23 TRACEPKT15 Data/address information output
25 TRACEPKT14 on pipeline status
24 TRACEPKT3
27 TRACEPKT13
28 TRACEPKT1
29 TRACEPKT12
30 TRACEPKT0
31 TRACEPKT11
32 TRACESYNC
33 TRACEPKT10
34 PIPESTAT2
35 TRACEPKT9
36 PIPESTAT1
37 TRACEPKT8
38 PIPESTAT0
26 TRACEPKT2
Processor pipeline status
39 GND
Ground
40 GND
Ground
41 GND
Ground
42 GND
Ground
43 GND
Ground
See Table 57 on page 66 for pin-out information for the ETM9 trace port.
54
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Configuration/Debugging Interfaces
On the development board, there are interfaces for a MasterBlaster or
ByteBlasterMV cable, and a Multi-ICE connector. Table 45 lists the signals
on the MasterBlaster/ByteBlasterMV interface.
Table 45. MasterBlaster/ByteBlasterMV Female Interface
Pin
JTAG Mode
Signal
Description
1
TCK
Clock signal
2
GND
Signal ground
3
TDO
Data from device
4
Vcc
Power supply
5
TMS
JTAG state machine control
6
Vio
Reference voltage for MasterBlaster/ByteBlasterMV output driver
7
TCK
Clock signal
8
–
No connection
9
TDI
Data to device
10
GND
Signal ground
See Table 47 on page 58 for pin-out information for the development
board configuration and debugging interfaces.
Altera Corporation
55
EPXA10 DDR Development Board Hardware Reference Manual
Table 46 lists the signals on the Multi-ICE interface.
Table 46. Multi-ICE Connector
Pin
Signal
Description
Direction
1 Vcc
Power supply
N/A
2 Vcc
Power supply
N/A
3 PROC_NTRTS
Processor reset
4 GND
Ground
5 PROC_TDI
Processor test data input
6 GND
Ground
7 PROC_TMS
Processor test mode select
8 GND
Ground
9 PROC_TCK
Processor test clock input
O
N/A
I
N/A
I
N/A
I
10 GND
Ground
N/A
11 GND
Ground
N/A
12 GND
Ground
N/A
13 PROC_TDO
Processor test data output
14 GND
Ground
N/A
15 NSRST
Warm reset
I/O
16 GND
Ground
N/A
17 NC
No connection
N/A
18 GND
Ground
N/A
19 NA
No connection
N/A
20 GND
Ground
N/A
O
See Table 47 on page 58 for pin-out information for the development
board configuration and debugging interfaces.
f
For signal details of the EPC16 device, refer to the EPC16 pin-out table.
See Table 57 on page 66 for pin-out information for the trace port.
56
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Pin-Outs
The main component of the development board is the EPXA10F1020C1
device. The pins on the EPXA10 device are assigned to functions on the
board. When generating IP cores for the EPXA10 device, the pins must be
used as defined to avoid damaging the device and any unused pins must
be tri-stated using the Quartus II software. The following sections list the
interfaces and dedicated pins on the board. Any pins not used for a design
should be left in the high-impedance (input) state to avoid contention.
This section details the EPXA10 device pins that are assigned to the
following purposes:
■
■
■
■
■
■
■
■
■
■
Configuration
DDR SDRAM
EBI
UARTs 1 and 2
Ethernet
User LEDs, push buttons, and dip-switches
Fast I/O pins
IDC 10-pin header
Trace port
Test points
Pin assignments are grouped into tables for control pins, bank address
pins, and data bus pins where appropriate. The tables also detail signals
passing across a connection. The remaining I/O pins on the EPXA10
device are listed at the end of this section.
Configuration
The EPXA10 device pins listed in Table 47 on page 58 are used exclusively
for configuring the device. Refer to “Device Configuration” on page 41 for
more information about EPXA10 configuration.
.
Altera Corporation
57
EPXA10 DDR Development Board Hardware Reference Manual
Table 47. EPXA10 Device Configuration Pins
Signal Name
EPXA10 Device Pin
Description
MSEL0
J30
Configuration mode select (tied to GND)
MSEL1
K30
Configuration mode select (tied to GND)
NSTATUS
AM14
OE for EPC16
NCONFIG
R30
n_INIT_CONF for EPC16
DCLK
W3
Data clock for EPC16
CONF_DONE
AM13
INIT_DONE
D14
Initialization complete indicator
nCE
AC3
Not connected
nCEO
D13
DATA0
V3
DATA1
D10
DATA2
A9
DATA3
B9
DATA4
C9
DATA5
D9
DATA6
A4
DATA7
B4
Configuration complete indicator
Serial input for EPC16 configuration data
Serial input for EPC16 configuration data; available for user I/O after
configuration
TDI
AD3
JTAG data input
TDO
E11
JTAG data output (to next device in the chain
TCK
AM19
JTAG clock
TMS
AM20
JTAG mode select
TRST
C13
JTAG reset (pulled high)
PROC_TDI
H27
JTAG data input
PROC_TDO
H26
JTAG data output (to next device in the chain
PROC_TCK
D30
JTAG clock
PROC_TMS
E29
JTAG mode select
PROC_TRST
E30
JTAG reset (pulled high)
H3
Global reset for the device
DEV_CLRn
DEV_OE
AE3
Device output enable
nWS
C4
Write strobe
nRS
D4
Read strobe
nCS
D3
Signal providing handshaking between devices
CS
E3
Chip select
RDYnBSY
E14
Ready/busy
CLKUSR
A13
Clock signal
58
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
DDR SDRAM Interface
There are four DDR chips (256-Mbit × 8) on the EPXA10 DDR
development board, selectable using one chip-select, SD_CS0_N. The
development board DDR interface can run at up to 266 MHz.
f
For more details on how to use the DDR SDRAM, ref to AN141: Using the
SDRAM Controller.
Table 48 lists the pin-outs for the DDR SDRAM control signals.
Table 48. DDR SDRAM Control Signal Pin-Outs
Signal Name
EPXA10 Device Pin
Description
F17
Row address strobe
SD_CAS_N
F18
Column address strobe
SD_WE_N
G18
Write enable
SD_CS0_N
G14
Chip select
SD_CS1_N
F16
Chip select
SD_CLKE
F14
Clock enable
SD_CLK
F15
SDRAM clock
SD_CLK_N
G13
SDRAM clock - inverted
SD_DQM(0)
H14
Data byte mask
SD_DQM(1)
L14
Data byte mask
SD_DQM(2)
K9
Data byte mask
SD_DQM(3)
H9
Data byte mask
SD_DQS(0)
J14
DQS signal
SD_DQS(1)
K14
DQS signal
SD_DQS(2)
K10
DQS signal
SD_DQS(3)
H10
DQS signal
SD_RAS_N
Table 49 on page 60 lists the DDR SDRAM data bank and address bus pinouts.
Altera Corporation
59
EPXA10 DDR Development Board Hardware Reference Manual
Table 49. DDR SDRAM Data Bank & Address Bus Pin-Outs
Signal Name
EPXA10 Device
Pin
Signal Name
EPXA10 Device
Pin
Signal Name
EPXA10 Device
Pin
SD_DQ0
H18
SD_DQ1
H17
SD_DQ2
H16
SD_DQ3
J18
SD_DQ4
J17
SD_DQ5
H15
SD_DQ6
J16
SD_DQ7
J15
SD_DQ8
K18
SD_DQ9
K17
SD_DQ10
L18
SD_DQ11
K16
SD_DQ12
L17
SD_DQ13
L16
SD_DQ14
K15
SD_DQ15
L15
SD_DQ16
L13
SD_DQ17
K13
SD_DQ18
L12
SD_DQ19
K12
SD_DQ20
L11
SD_DQ21
K11
SD_DQ22
L10
SD_DQ23
L9
SD_DQ24
H13
SD_DQ25
H12
SD_DQ26
J13
SD_DQ27
J12
SD_DQ28
J11
SD_DQ29
J10
SD_DQ30
J9
SD_DQ31
H11
SD_ADD0
G12
SD_ADD1
F13
SD_ADD2
G11
SD_ADD3
F12
SD_ADD4
F11
SD_ADD5
G10
SD_ADD6
F10
SD_ADD7
F9
SD_ADD8
G9
SD_ADD9
F8
SD_ADD10
G8
SD_ADD11
F7
SD_ADD12
F6
SD_ADD13
G7
SD_ADD14
G6
60
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
EBI
Table 50 lists the EPXA10 pin-outs for the EBI control signals.
Table 50. EBI Control Signal Pin-Outs
Signal Name
Altera Corporation
EPXA10 Device Pin
Description
EBI_BE0
F27
Byte enable
EBI_BE1
E27
Byte enable
EBI_OE
F26
Output enable
EBI_WE
E26
Write enable
EBI_CS0
A25
Chip select
EBI_CS1
B25
Chip select
EBI_CS2
C25
Chip select
EBI_CS3
D25
Chip select
EBI_CLK
E25
EBI clock
EBI_ACK
F25
EBI acknowledge
INT_EXTPIN_N
G25
Interrupt generated by push-button SW4
61
EPXA10 DDR Development Board Hardware Reference Manual
Table 51 lists the EBI data bank and address bus pin-outs.
Table 51. EBI Data Bank and Address Bus Pin-Outs
Signal Name
62
EPXA10 Device
Pin
Signal Name
EPXA10 Device
Pin
EBI_DQ0
J21
EBI_DQ1
H21
EBI_DQ2
E20
EBI_DQ3
F20
EBI_DQ4
E19
EBI_DQ5
L20
EBI_DQ6
K20
EBI_DQ7
J20
EBI_DQ8
H20
EBI_DQ9
G20
EBI_DQ10
F19
EBI_DQ11
G19
EBI_DQ12
L19
EBI_DQ13
K19
EBI_DQ14
J19
EBI_DQ15
H19
EBI_A0
H25
EBI_A1
D24
EBI_A2
E24
EBI_A3
F24
EBI_A4
G24
EBI_A5
J24
EBI_A6
H24
EBI_A7
E23
EBI_A8
F23
EBI_A9
G23
EBI_A10
K23
EBI_A11
J23
EBI_A12
H23
EBI_A13
E22
EBI_A14
F22
EBI_A15
E21
EBI_A16
L22
EBI_A17
K22
EBI_A18
J22
EBI_A19
H22
EBI_A20
G22
EBI_A21
F21
EBI_A22
G21
EBI_A23
L21
EBI_A24
K21
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
PCI
Table 52 lists the pins used for the PCI cards.
Table 52. PCI Pin-Outs
FPGA UART
Embedded Stripe UART
EPXA10 Device Device Signal (Board EPXA10 Device Device Signal (Board
Pin
Signal)
Pin
Signal)
Altera Corporation
AF21
C/BE0#
AF22
A5 (PCI_BUS5)
AE19
C/BE1#
AG22
A6 (PCI_BUS6)
AF19
C/BE2#
AH22
A7 (PCI_BUS7)
AJ18
C/BE3#
AD21
A8 (PCI_BUS8)
AG19
DEVSEL#
AE21
A9 (PCI_BUS9)
AH19
FRAME#
AG21
A10 (PCI_BUS10)
AB20
GNT1#
AH21
A11 (PCI_BUS11)
AC20
GNT2#
AD20
A12 (PCI_BUS12)
AB22
INTA#
AE20
A13 (PCI_BUS13)
AG23
INTB#
AF20
A14 (PCI_BUS14)
AC22
INTC#
AH20
A15 (PCI_BUS15)
AF23
INTD#
AJ19
A16 (PCI_BUS16)
AK20
PAR
AK19
A17 (PCI_BUS17)
AB18
PCI_RST#
AL19
A18 (PCI_BUS18)
AL18
PERR#
AD18
A19 (PCI_BUS19)
AB21
PRSNT1#
AE18
A20 (PCI_BUS20)
AC22
PRSNT2#
AF18
A21 (PCI_BUS21)
AD19
REQ1#
AG18
A22 (PCI_BUS22)
AC19
REQ2#
AH18
A23 (PCI_BUS23)
AB19
SERR#
AK18
A24 (PCI_BUS24)
AB17
STOP#
AC17
A25 (PCI_BUS25)
AC18
TRDY#
AD17
A26 (PCI_BUS26)
AK23
A0 (PCI_BUS0)
AE17
A27 (PCI_BUS27)
AL23
A1 (PCI_BUS1)
AF17
A28 (PCI_BUS28)
AM23
A2 (PCI_BUS2)
AG17
A29 (PCI_BUS29)
AD22
A3 (PCI_BUS3)
AH17
A30 (PCI_BUS30)
AE22
A4 (PCI_BUS4)
AJ17
A31 (PCI_BUS31)
63
EPXA10 DDR Development Board Hardware Reference Manual
UART1 & UART2
Table 53 lists the pins used for UARTs 1 and 2.
Table 53. Extension Header UARTs 1 & 2 I/O Pin-Outs
FPGA UART
EPXA10 Device
Pin
Device Signal
Embedded Stripe UART
Expansion Board
Connector
EPXA10 Device
Pin
Device Signal
Expansion Board
Connector
J27
UART2_DTR_N
U16.171
G28
UART1_CTS_N
NC
J29
UART2_TXD
U16.174
D29
UART1_RXD
NC
K29
UART2_RXD_N
U16.177
E28
UART1_RI_N
NC
K27
UART2_DSR_N
U16.179
C28
UART1_RTS_N
NC
J28
UART2_RTS_N
U16.173
F28
UART1_DSR_N
NC
J26
UART2_RI_N
U16.175
G27
UART1_DCD_N
NC
K28
UART2_DCD_N
U16.178
D28
UART1_TXD
NC
K26
UART2_CTS_N
U16.181
G26
UART1_DTR_N
NC
Ethernet
Table 53 lists the pins used for the Ethernet interface.
Table 54. Extension Header Ethernet Pin-Outs
EPXA10 Device
Pin
64
Device Signal
Expansion Board
Connector
EPXA10 Device
Pin
Device Signal
Expansion Board
Connector
R23
RXD1
U16.155
R24
TXD3
U16.153
R25
TXD0
U16.149
M19
MDC
U16.145
M20
RST_N
U16.146
M21
TX_ER
U16.161
M22
TX_EN
U16.162
M23
RXD2
U16.157
N19
CRS
U16.166
N20
COL
U16.163
N21
RX_DV
U16.167
N22
MDIO
U16.169
N23
RXD0
U16.154
P20
INTR
U16.147
P21
RX_ER
U16.165
P22
RX_D3
U16.158
N25
TXD1
U16.150
P25
TXD2
U16.151
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Fast I/O Pins
Table 55 lists the pins used for the EPXA10 fast I/O pins.
Table 55. EPXA10 Fast I/O Pins
EPXA10 Pin
Name
Description
EPXA10
Device Pin
Expansion Board
Connector
Board
Reference
FAST0
Dedicated fast I/O pins
E13
U16.133
FAST0
FAST1
Dedicated fast I/O pins
E12
U16.134
FAST1
FAST2
Dedicated fast I/O pins
AM18
U16.135
FAST2
FAST3
Connected to PCI to provide IRDY#
AM15
IRDY#
User LEDs, Switches & Push Button Switches
Table 56 lists the pins used for the user-defined LEDs, push-button
switches and dip-switches.
Table 56. Expansion Header LED, Switch and Push Button I/O Pin-Outs
EPXA10
Device Pin
Device Signal
Expansion Board
Connector
EPXA10
Device Pin
Device Signal
Board Connector
V6
USER_LED0
U18.1
U5
USER_LED1
U18.3
V5
USER_LED2
U18.4
U6
USER_LED3
U18.5
V7
USER_LED4
U18.7
V8
USER_LED5
U18.8
U7
USER_LED6
U18.9
T6
USER_LED7
U18.11
U8
USER_SW0
U18.12
T5
USER_SW1
U18.13
V4
USER_SW2
U18.15
V10
USER_SW3
U18.16
T7
USER_SW4
U18.17
W12
USER_SW5
U18.17
U9
USER_SW6
U18.20
V11
USER_SW7
U18.21
R6
USER-SW8
U18.23
T8
USER_PB0
U18.24
R5
USER_PB1
U18.25
U4
USER_PB2
U18.27
U10
USER_PB3
U18.28
Altera Corporation
65
EPXA10 DDR Development Board Hardware Reference Manual
Trace Port
Table 57 lists the pins used on the trace port interface.
Table 57. Trace Port Pin-Out
EPXA10 Device
Pin
Device Signal
EPXA10 Device
Pin
Device Signal
H6
TRACEPKT15
N7
TRACEPKT4
J6
TRACEPKT14
H8
TRACEPKT3
K6
TRACEPKT13
J8
TRACEPKT2
L6
TRACEPKT12
K8
TRACEPKT1
M6
TRACEPKT11
L8
TRACEPKT0
N6
TRACEPKT10
M8
TRACESYNC
H7
TRACEPKT9
M9
PIPESTAT2
J7
TRACEPKT8
N9
PIPESTAT1
K7
TRACEPKT7
N10
PIPESTAT0
L7
TRACEPKT6
N8
TRACECLK
M7
TRACEPKT5
IDC 10-Pin Header
Table 56 lists the pins used for the 10-pin IDC header.
Table 58. IDC Header Pin-Outs
EPXA10 Device Pin
66
Header Pin
Expansion Board
Connector
L5
Header1.1
U18.71
K4
Header1.2
U18.72
J4
Header1.3
U18.73
H4
Header1.4
U18.75
K5
Header1.5
U18.76
E4
Header1.6
U18.77
J5
Header1.7
U18.79
H5
Header1.8
U18.80
GND
Header1.9
n/a
GND
Header1.10
n/a
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Expansion Header
The pins on the expansion header cards connect to I/O pins on the
EPXA10 device, to ground or to VCC supplies.
I/O Pin-Outs
Tables 59 to 62 list the pins on the EPXA10 DDR development board
expansion header cards that connect to I/O pins on the EPXA10 device.
Some of these pins can optionally be dedicated to the Ethernet, UART,
user LEDs, push-button switches, and dip-switches.
Table 59. Development Board Expansion Header U15 I/O Pin-Outs (Part 1 of 2)
U15.1-50
Device
U15.51-100
Device
U15.
101-150
Device
U15.
151-200
Device
U15.1
AB24
U15.51
AC23
U15.101
GND
U15.151
Y5
U15.2
GND
U15.52
AD23
U15.102
W4
U15.152
Y8
U15.3
L24
U15.53
AE23
U15.103
W5
U15.153
GND
U15.4
L26
U15.54
GND
U15.104
AA6
U15.154
Y7
U15.5
L27
U15.55
AL20
U15.105
GND
U15.155
Y4
U15.6
GND
U15.56
AJ20
U15.106
W8
U15.156
B24
U15.7
AJ29
U15.57
AG20
U15.107
Y6
U15.157
GND
U15.8
AK29
U15.58
GND
U15.108
W7
U15.158
A24
U15.9
AH28
U15.59
AJ30
U15.109
GND
U15.159
D23
U15.10
GND
U15.60
IO/Data7
U15.110
W6
U15.160
C23
U15.11
AJ28
U15.61
IO/Data6
U15.111
AF5
U15.161
GND
U15.12
AK28
U15.62
GND
U15.112
AE4
U15.162
B23
U15.13
AH27
U15.63
IO/Data5
U15.113
GND
U15.163
A23
U15.14
GND
U15.64
IO/Data4
U15.114
AD4
U15.164
D20
U15.15
AH26
U15.65
IO/Data3
U15.115
AC4
U15.165
GND
U15.16
AG26
U15.66
GND
U15.116
AE5
U15.166
C20
U15.17
AF26
U15.67
IO/Data2
U15.117
GND
U15.167
B20
U15.18
GND
U15.68
IO/Data1
U15.118
AD8
U15.168
A20
U15.19
AM25(1)
U15.69
N26
U15.119
AA12
U15.169
GND
U15.20
AL25
U15.70
GND
U15.120
AC9
U15.170
D19
U15.21
AK25(1)
U15.71
N29
U15.121
GND
U15.171
C19
U15.22
GND
U15.72
IO/CLKUSR
U15.122
AD5
U15.172
B19
U15.23
AJ25(1)
U15.73
IO/RDYNBSY U15.123
AC5
U15.173
GND
U15.24
AH25
U15.74
GND
U15.124
AD7
U15.174
A19
U15.25
AG25
U15.75
NRS
U15.125
GND
U15.175
A18
Altera Corporation
67
EPXA10 DDR Development Board Hardware Reference Manual
Table 59. Development Board Expansion Header U15 I/O Pin-Outs (Part 2 of 2)
U15.1-50
Device
U15.51-100
Device
U15.
101-150
Device
U15.
151-200
Device
U15.26
GND
U15.76
IO/NWS
U15.126
AA11
U15.176
B18
U15.27
AF25
U15.77
IO/NCS
U15.127
Y12
U15.177
GND
U15.28
AE25
U15.78
GND
U15.128
AC8
U15.178
D18
U15.29
AD25
U15.79
IO/CS
U15.129
GND
U15.179
E18
U15.30
GND
U15.80
M25
U15.130
AB5
U15.180
D17
U15.31
AC25
U15.80
M26
U15.131
AB9
U15.181
GND
U15.32
AB25
U15.81
P27
U15.132
AA10
U15.182
E17
U15.33
AM24
U15.82
GND
U15.133
GND
U15.183
D16
U15.34
GND
U15.83
M28
U15.134
Y11
U15.184
E16
U15.35
AL24
U15.84
NC
U15.135
AD6
U15.185
GND
U15.36
AK24
U15.85
NC
U15.136
AA5
U15.186
D15
U15.37
AJ24
U15.86
GND
U15.137
GND
U15.187
B15
U15.38
GND
U15.87
NCLK3
U15.138
AC7
U15.188
A15
U15.39
AH24
U15.88
GND
U15.139
AB8
U15.189
GND
U15.40
AC24
U15.89
NCLK4
U15.140
Y10
U15.190
B14
U15.41
AD24
U15.90
GND
U15.141
GND
U15.191
A14
U15.42
GND
U15.91
CLK2_OUT
U15.142
W11
U15.192
E15
U15.43
AE24
U15.92
GND
U15.143
AA8
U15.193
GND
U15.44
AF24
U15.93
NCLK2_FB
U15.144
AB7
U15.194
C14
U15.45
AG24
U15.94
GND
U15.145
GND
U15.195
NCLK1_FB
U15.46
GND
U15.95
CLK2_FBP
U15.146
AC6
U15.196
GND
U15.47
AJ23
U15.96
GND
U15.147
W10
U15.197
CLK1_FBP
U15.48
AH23
U15.97
NCLK2
U15.148
AA7
U15.198
GND
U15.49
AB23
U15.98
GND
U15.149
GND
U15.199
NCLK1
U15.50
GND
U15.99
CLK1_OUT
U15.150
AB6
U15.200
GND
68
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
.
Table 60. Development Board Expansion Header U16 I/O Pin-Outs (Part 1 of 2)
U16.1-50
Device
U16.51100
Device
U16.
101-150
Device
U16.
151-200
Device
U16.1
GND
U16.51
AD2
U16.101
IO/LVDSDSKW U16.151
P25
U16.2
AE3
U16.52
GND
U16.102
GND
U16.152
GND
U16.3
AK5
U16.53
AE1
U16.103
W32
U16.153
R24
U16.4
GND
U16.54
AE2
U16.104
W31
U16.154
N23
U16.5
AM5
U16.55
GND
U16.105
GND
U16.155
R23
U16.6
AL5
U16.56
AH1
U16.106
V31
U16.156
GND
U16.7
GND
U16.57
AH2
U16.107
V32
U16.157
M23
U16.8
AK4
U16.58
GND
U16.108
GND
U16.158
P22
U16.9
AJ3
U16.59
AJ1
U16.109
R32
U16.159
NC
U16.10
GND
U16.60
AJ2
U16.110
R31
U16.160
GND
U16.11
AL4
U16.61
GND
U16.111
GND
U16.161
M21
U16.12
AM4
U16.62
B29
U16.112
P31
U16.162
M22
U16.13
GND
U16.63
A29
U16.113
P32
U16.163
N20
U16.14
D1
U16.64
GND
U16.114
GND
U16.164
GND
U16.15
D2
U16.65
AJ32
U16.115
N32
U16.165
P21
U16.16
GND
U16.66
AJ31
U16.116
N31
U16.166
N19
U16.17
E1
U16.67
GND
U16.117
GND
U16.167
N21
U16.18
E2
U16.68
AH31
U16.118
K31
U16.168
GND
U16.19
GND
U16.69
AH32
U16.119
K32
U16.169
N22
U16.20
H1
U16.70
GND
U16.120
GND
U16.170
J26
U16.21
H2
U16.71
AE32
U16.121
J32
U16.171
J27
U16.22
GND
U16.72
AE31
U16.122
J31
U16.172
GND
U16.23
J1
U16.73
GND
U16.123
GND
U16.173
J28
U16.24
J2
U16.74
AD31
U16.124
H31
U16.174
J29
U16.25
GND
U16.75
AD32
U16.125
H32
U16.175
UART2_RI_N
U16.26
K1
U16.76
GND
U16.126
GND
U16.176
GND
U16.27
K2
U16.77
AC32
U16.127
E32
U16.177
K29
U16.28
GND
U16.78
AC31
U16.128
E31
U16.178
K28
U16.29
N2
U16.79
GND
U16.129
GND
U16.179
K27
U16.30
N1
U16.80
Y31
U16.130
D31
U16.180
GND
U16.31
GND
U16.81
Y32
U16.131
D32
U16.181
K26
U16.32
P1
U16.82
GND
U16.132
GND
U16.182
L28
U16.33
P2
U16.83
AC30
U16.133
FAST0
U16.183
L23
U16.34
GND
U16.84
AL29
U16.134
FAST1
U16.184
GND
Altera Corporation
69
EPXA10 DDR Development Board Hardware Reference Manual
Table 60. Development Board Expansion Header U16 I/O Pin-Outs (Part 2 of 2)
U16.1-50
Device
U16.51100
Device
U16.
101-150
Device
U16.
151-200
Device
U16.35
R1
U16.85
H30
U16.135
FAST2
U16.185
GND
U16.36
R2
U16.86
GND
U16.136
GND
U16.186
12V
U16.37
GND
U16.87
5V
U16.137
R26
U16.187
3.3V
U16.38
V1
U16.88
3.3V
U16.138
R27
U16.188
12V-
U16.39
V2
U16.89
5V
U16.139
R28
U16.189
3.3V
U16.40
GND
U16.90
3.3V
U16.140
GND
U16.190
12V-
U16.41
W1
U16.91
5V
U16.141
R29
U16.191
3.3V
U16.42
W2
U16.92
3.3V
U16.142
P28
U16.192
12V
U16.43
GND
U16.93
5V
U16.143
P29
U16.193
3.3V
U16.44
Y2
U16.94
3.3V
U16.144
GND
U16.194
12V
U16.45
Y1
U16.95
5V
U16.145
M19
U16.195
3.3V
U16.46
GND
U16.96
3.3V
U16.146
M20
U16.196
12V
U16.47
AC1
U16.97
5V
U16.147
P20
U16.197
3.3V
U16.48
AC2
U16.98
3.3V
U16.148
GND
U16.198
12V
U16.49
GND
U16.99
5V
U16.149
R25
U16.199
3.3V
U16.50
AD1
U16.100
3.3V
U16.150
N25
U16.200
12V
70
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
.
Table 61. Development Board Expansion Header U17 I/O Pin-Outs (Part 1 of 2)
U17.1-50
Device
U17.51-100
Device
U17.
101-150
Device
U17.
151-200
Device
U17.1
AC11
U17.51
AJ5
U17.101
GND
U17.151
W22
U17.2
GND
U17.52
AH5
U17.102
NC
U17.152
V21
U17.3
AB11
U17.53
AJ4
U17.103
NRESET
U17.153
GND
U17.4
AH10
U17.54
GND
U17.104
NC
U17.154
AA28
U17.5
AJ10
U17.55
AH4
U17.105
GND
U17.155
AC27
U17.6
GND
U17.56
AG5
U17.106
NC
U17.156
AB26
U17.7
AK10
U17.57
T27
U17.107
NC
U17.157
GND
U17.8
AL10
U17.58
GND
U17.108
NC
U17.158
AA25
U17.9
AG10
U17.59
U27
U17.109
GND
U17.159
Y24
U17.10
GND
U17.60
V27
U17.110
NC
U17.160
W23
U17.11
AF10
U17.61
V26
U17.111
NC
U17.161
GND
U17.12
AE10
U17.62
GND
U17.112
NC
U17.162
V22
U17.13
AD10
U17.63
T29
U17.113
GND
U17.163
U21
U17.14
GND
U17.64
T28
U17.114
AG28
U17.164
AB28
U17.15
AC10
U17.65
T26
U17.115
AH29
U17.165
GND
U17.16
AB10
U17.66
GND
U17.116
AG27
U17.166
Y28
U17.17
AH9
U17.67
U26
U17.117
GND
U17.167
AB27
U17.18
GND
U17.68
W27
U17.118
AH30
U17.168
AA26
U17.19
AJ9
U17.69
T25
U17.119
AF27
U17.169
GND
U17.20
AK9
U17.70
GND
U17.120
AF28
U17.170
Y25
U17.21
AL9
U17.71
U25
U17.121
GND
U17.171
V23
U17.22
GND
U17.72
U29
U17.122
AE26
U17.172
U22
U17.23
AM9
U17.73
U28
U17.123
AE27
U17.173
GND
U17.24
AG9
U17.74
GND
U17.124
AE30
U17.174
T21
U17.25
AF9
U17.75
R22
U17.125
GND
U17.175
W28
U17.26
GND
U17.76
Y27
U17.126
AE29
U17.176
W29
U17.27
AE9
U17.77
W26
U17.127
AE28
U17.177
GND
U17.28
AD9
U17.78
GND
U17.128
AA21
U17.178
R20
U17.29
AM8
U17.79
V25
U17.129
GND
U17.179
T22
U17.30
GND
U17.80
U24
U17.130
AD26
U17.180
AA27
U17.31
AL8
U17.81
T23
U17.131
AD30
U17.181
GND
U17.32
AK8
U17.82
GND
U17.132
AD29
U17.182
Y26
U17.33
AJ8
U17.83
R21
U17.133
GND
U17.183
W25
U17.34
GND
U17.84
V29
U17.134
AC29
U17.184
U23
Altera Corporation
71
EPXA10 DDR Development Board Hardware Reference Manual
Table 61. Development Board Expansion Header U17 I/O Pin-Outs (Part 2 of 2)
U17.1-50
Device
U17.51-100
Device
U17.
101-150
Device
U17.
151-200
Device
U17.35
AH8
U17.85
V28
U17.135
AA22
U17.185
GND
U17.36
AG8
U17.86
GND
U17.136
AD27
U17.186
12V
U17.37
AF8
U17.87
5V
U17.137
GND
U17.187
3.3V
U17.38
GND
U17.88
3.3V
U17.138
AD28
U17.188
12V-
U17.39
AE8
U17.89
5V
U17.139
Y29
U17.189
3.3V
U17.40
AH7
U17.90
3.3V
U17.140
Y21
U17.190
12V-
U17.41
AF7
U17.91
5V
U17.141
GND
U17.191
3.3V
U17.42
GND
U17.92
3.3V
U17.142
AA23
U17.192
12V
U17.43
AG7
U17.93
5V
U17.143
AC28
U17.193
3.3V
U17.44
AE7
U17.94
3.3V
U17.144
AC26
U17.194
12V
U17.45
AH6
U17.95
5V
U17.145
GND
U17.195
3.3V
U17.46
GND
U17.96
3.3V
U17.146
Y22
U17.196
12V
U17.47
AG6
U17.97
5V
U17.147
W21
U17.197
3.3V
U17.48
AF6
U17.98
3.3V
U17.148
AA24
U17.198
12V
U17.49
AE6
U17.99
5V
U17.149
GND
U17.199
3.3V
U17.50
GND
U17.100
3.3V
U17.150
Y23
U17.200
12V
72
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
.
Table 62. Development Board Expansion Header U18 I/O Pin-Outs (Part 1 of 2)
U18.1-50
Device
U18.51-100
Device
U18.
101-150
Device
U18.
151-200
Device
U18.1
V6
U18.51
N5
U18.101
GND
U18.151
AF13
U18.2
GND
U18.52
R10
U18.102
AK17
U18.152
AG13
U18.3
U5
U18.53
R11
U18.103
AK16
U18.153
GND
U18.4
V5
U18.54
GND
U18.104
AJ16
U18.154
AB13
U18.5
U6
U18.55
R12
U18.105
GND
U18.155
AH12
U18.6
GND
U18.56
R13
U18.106
AH16
U18.156
AE12
U18.7
V7
U18.57
P10
U18.107
AG16
U18.157
GND
U18.8
V8
U18.58
GND
U18.108
AF16
U18.158
AF12
U18.9
U7
U18.59
P11
U18.109
GND
U18.159
AG12
U18.10
GND
U18.60
P12
U18.110
AE16
U18.160
AG11
U18.11
T6
U18.61
P13
U18.111
AD16
U18.161
GND
U18.12
U8
U18.62
GND
U18.112
AC16
U18.162
AD12
U18.13
T5
U18.63
P4
U18.113
GND
U18.163
AF11
U18.14
GND
U18.64
N4
U18.114
AB16
U18.164
AH11
U18.15
V4
U18.65
N11
U18.115
AL15
U18.165
GND
U18.16
V10
U18.66
GND
U18.116
AK15
U18.166
AC12
U18.17
T7
U18.67
N12
U18.117
GND
U18.167
AE11
U18.17
W12
U18.68
N13
U18.118
AJ15
U18.168
AB12
U18.18
GND
U18.69
M5
U18.119
AH15
U18.169
GND
U18.19
USER_SW5 U18.70
GND
U18.120
AG15
U18.170
AD11
U18.20
U9
U18.71
L5
U18.121
GND
U18.171
A8
U18.21
V11
U18.72
K4
U18.122
AF15
U18.172
E6
U18.22
GND
U18.73
J4
U18.123
AE15
U18.173
GND
U18.23
R6
U18.74
GND
U18.124
AD15
U18.174
E7
U18.24
T8
U18.75
H4
U18.125
GND
U18.175
C8
U18.25
R5
U18.76
K5
U18.126
AC15
U18.176
B8
U18.26
GND
U18.77
E4
U18.127
AB15
U18.177
GND
U18.27
U4
U18.78
GND
U18.128
AL14
U18.178
E9
U18.28
U10
U18.79
J5
U18.129
GND
U18.179
E8
U18.29
R7
U18.80
H5
U18.130
AK14
U18.180
D8
U18.30
GND
U18.81
G5
U18.131
AJ14
U18.181
GND
U18.31
V12
U18.82
GND
U18.132
AH14
U18.182
B5
U18.32
U11
U18.83
F5
U18.133
GND
U18.183
A5
U18.33
R8
U18.84
E5
U18.134
AG14
U18.184
E10
Altera Corporation
73
EPXA10 DDR Development Board Hardware Reference Manual
Table 62. Development Board Expansion Header U18 I/O Pin-Outs (Part 2 of 2)
U18.1-50
Device
U18.51-100
Device
U18.
101-150
Device
U18.
151-200
Device
U18.34
GND
U18.85
D5
U18.135
AF14
U18.185
GND
U18.35
P6
U18.86
GND
U18.136
AE14
U18.186
12V
U18.36
T4
U18.87
5V
U18.137
GND
U18.187
3.3V
U18.37
P5
U18.88
3.3V
U18.138
AD14
U18.188
12V-
U18.38
GND
U18.89
5V
U18.139
AC14
U18.189
3.3V
U18.39
T10
U18.90
3.3V
U18.140
AB14
U18.190
12V-
U18.40
U12
U18.91
5V
U18.141
GND
U18.191
3.3V
U18.41
T11
U18.92
3.3V
U18.142
AL13
U18.192
12V
U18.42
GND
U18.93
5V
U18.143
AK13
U18.193
3.3V
U18.43
P7
U18.94
3.3V
U18.144
AJ13
U18.194
12V
U18.44
R9
U18.95
5V
U18.145
GND
U18.195
3.3V
U18.45
T12
U18.96
3.3V
U18.146
AH13
U18.196
12V
U18.46
GND
U18.97
5V
U18.147
AC13
U18.197
3.3V
U18.47
T13
U18.98
3.3V
U18.148
AD13
U18.198
12V
U18.48
P8
U18.99
5V
U18.149
GND
U18.199
3.3V
U18.49
R4
U18.100
3.3V
U18.150
AE13
U18.200
12V
U18.50
GND
U18.51
N5
U18.101
GND
U18.151
AF13
GND Connections
Table 59 lists the pins on the EPXA10 DDR development board expansion
header cards that connect to GND.
Table 63. Development Board Expansion Header GND Connections
Header
Pin
U15
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 88, 90, 92, 94, 96,
98, 100, 101, 105, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169,
173, 177, 181, 185, 189, 193, 196, 198, 200
U16
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 43, 46, 49, 52, 55, 58, 61, 64, 67, 70, 73, 76, 79,
82, 86, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 136, 140, 144, 148, 152, 156, 160,
164, 168, 172, 176, 180, 184, 185
U17
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 101, 105, 109, 113,
117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185
U18
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 101, 105, 109, 113,
117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185
74
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
VCC Connections
Table 59 lists the pins on the EPXA10 DDR development board expansion
header cards that connect to VCC power supplies.
Table 64. Development Board Expansion Header VC C Connections
Expansion
Header
U16
U17
U18
VC C
Pin
3.3 V
88, 90, 92, 94, 96, 98, 100, 187, 189, 191, 193, 195, 197, 199
5V
87, 89, 91, 93, 95, 97, 99
12 V
186, 192, 194, 196, 198, 200
–12 V
188, 190
3.3 V
88, 90, 92, 94, 96, 98, 100, 187, 189, 191, 193, 195, 197, 199
5V
87, 89, 91, 93, 95, 97, 99
12 V
186, 192, 194, 196, 198, 200
–12 V
188, 190
3.3 V
88, 90, 92, 94, 96, 98, 100, 187, 189, 191, 193, 195, 197, 199
5V
87, 89, 91, 93, 95, 97, 99
12 V
186, 192, 194, 196, 198, 200
–12 V
188, 190
Altera Corporation
75
EPXA10 DDR Development Board Hardware Reference Manual
General Usage
Guidelines
To use the development board properly, and to avoid damage to it, follow
the guidelines in this section.
Anti-Static Handling
Before handling the card, you should take proper anti-static precautions,
otherwise the board can be damaged.
Power-Up
When power is initially applied to the board, the LEDs flash according to
the software test running on the embedded processor. The test suite is
programmed directly into flash memory, and when the embedded
processor boots it configures the FPGA and runs the software using the
test image.
Power Consumption
Power consumption issues need to be addressed only if the board is
powered from a terminal strip and not the provided ATX power supply
adaptor. Altera recommends that you monitor the input current to ensure
that sufficient power is supplied. The power required by the board is
directly related to the following:
■
■
■
Number of interfaces used
Density and speed of the device
Population of the interfaces
The typical maximum current is 5.0 A, which can be exceeded if the board
is heavily loaded with many interfaces running at high-clock speeds.
PCI Cards
1
Do not use 5-V PCI cards.
The PCI slots on the development board are suitable only for 3.3-V and
universal PCI cards. The keying slots on 5-V PCI cards are not designed to
mate with the motherboard connectors, because the signalling voltage on
5-V cards is incorrect for the development board.
76
Altera Corporation
EPXA10 DDR Development Board Hardware Reference Manual
Unused EPXA10 Device Pins
All unused general-purpose I/O EPXA10 device pins have been allocated
to the expansion headers. To avoid unnecessary power consumption and
possible contention, unused pins must be left in the high impedance
(input) state. Follow the steps below to put the unused EPXA10 device
pins into a high-impedance state:
1.
Run the Quartus II software.
2.
Choose Compiler Settings (Processing menu).
3.
Click the Chips & Devices tag.
4.
Click the Device & Pin Options button.
5.
Click the Unused Pins tag.
6.
Under Reserve all unused pins, select As inputs, tri-stated.
All the critical control lines for the interfaces on the board are pulled
to the inactive state.
1
If a device is not used, it can be ignored and the EPXA10 device
interface pins left as inputs.
Test Core Functionality
For implementing a test plan, Altera provides test cores with the
development board, which can be programmed onto the EPXA10 device
using the JTAG chain. Each test core tests one or more interfaces (pushbuttons, LEDs, switches, etc.). Diagnostic software is also provided to test
the board, the EPXA10 device, and its test cores, with results displayed on
a terminal.
Altera Corporation
77
EPXA10 DDR Development Board Hardware Reference Manual
78
Altera Corporation