HardCopy
ASIC Gain without the Pain
June 2003
Altera Corporation is the world’s pioneer in system-ona-programmable-chip (SOPC) solutions. Combining
programmable logic technology with integrated software tools, intellectual property (IP), embedded
processors, peripherals, and design services, Altera
provides high-value programmable solutions that
meet almost any design need. The inherent value of
programmable logic—cost and time-to-market advantages, low risk, and flexibility—uniquely position
Altera’s products to displace other more costly and
high-risk solutions, such as ASICs and ASSPs. Today,
Altera FPGAs offer a viable, more flexible alternative
to digital signal processors, thereby delivering value to
a
much
broader
market
than
was
previously
addressed by programmable logic. To learn more
about Altera’s complete SOPC solutions, visit the Altera
web site at www.altera.com.
A comprehensive alternative to
ASICs, Altera® HardCopy™
devices are the industry’s only
complete prototype-to-volumeproduction solution for highdensity designs. Engineers now have the option to
target either an FPGA or a high-volume maskprogrammed design at the beginning of the design
process using the same architecture, software, and
intellectual property (IP). Designers can completely
bypass the pain and expense of ASIC development
by using an Altera FPGA to prototype and verify
in-system and then seamlessly migrate that FPGAproven design to a HardCopy device for high-volume
production. HardCopy devices not only have the
ability to help manage rising costs, risks, and market
uncertainty, they also guarantee first-time success in
silicon and can boost performance an average of 50%
and lower power consumption up to 40% compared
to the original FPGA.
Eliminate ASIC Risk
In today’s market, high-volume applications require a
quick, easy-to-use, and low-cost solution that
provides enough performance and flexibility to tackle
the toughest product development challenges. ASICs,
once considered the ideal solution for high-volume
system-on-a-chip (SOC) applications, have become
less advantageous and more problematic with their
lengthy design and development times, numerous
risks, and escalating non-recurring engineering (NRE),
mask, and tool costs (see Figure 1).
Today’s SOC designs demand increasingly complex
embedded functions, IP, and logic, plus the flexibility
to keep up with rapidly evolving technology and
standards. Developing state-of-the-art designs on
ASICs requires an enormous budget and months of
engineering resources, a hefty investment that
necessitates success with the first silicon produced.
When an ASIC re-spin is necessary, companies not
only have to bear additional development and
engineering costs, they also lose time-to-market
advantages and prospective market opportunities.
Altera’s HardCopy devices present a painless
migration path that puts the power to manage rising
costs, risks, and market uncertainty back in designers’
hands. Extending the flexibility and time-to-market
advantages of high-density FPGAs, HardCopy devices
provide a low-cost, time-saving alternative to ASICs
that guarantees first-time success.
Only Altera’s HardCopy device family directly
addresses ASIC pains with these unparalleled features
and benefits:
■
FPGA-proven process technology and in-system
verified netlist
■
Single design flow, architecture, tools, and IP
■
Seamless migration process
■
Guaranteed success with first silicon produced
■
Low development costs
■
Fastest time-to-market
Figure 1. Rising ASIC Costs
14
0.09 µm
12
0.13 µm
10
$ (in Millions)
ASIC Gain without the Pain
0.18 µm
8
0.25 µm
6
4
0.35 µm
2
0
1995
Mask & Wafers
Altera Corporation
0.15 µm
1997
1999
Engineering
2000
2001
2003
Total Development Costs
3
Reduce Total Cost of Ownership
HardCopy devices are mask-programmed devices
created from a direct mapping of the FPGA
architecture. To generate HardCopy devices, Altera
uses common base arrays across multiple designs
for a particular density and implements customerspecific design information with the top metal layers
(the top two layers for HardCopy Stratix™ devices,
and the top three layers for HardCopy APEX 20KE™
and HardCopy APEX 20KC™ devices). This process
reduces the die size up to 70 percent, considerably
lowering unit costs and improving performance and
power consumption compared to the original FPGA.
These advantages, along with the following list,
greatly reduce overall development costs:
■
■
■
■
the FPGA-proven netlist, and ensures consistency
with the original designs. This seamless migration
process (see Figure 2) minimizes risk, guarantees
first-time success, and accelerates time-to-market.
With an easy migration process and minimal customer
involvement, Altera HardCopy devices can deliver
guaranteed fully operational prototypes and production
units in the shortest time possible (see Figure 3).
Figure 2. Seamless Migration
Provide FPGA Design File (*.sof)
Generate Netlist
Check for Test & Fix
Generate Automated
Test Patterns
Inexpensive design software
Guaranteed first-silicon success (no costly ASIC
re-spins)
Provide Constraint Files
Place-and-Route1
Review Results & Sign Off
Verify Timing
Fabricate Prototypes
No licensing or royalty fees for Altera MegaCore®
functions
Assemble & Test
Minimal NRE and mask costs
Minimize Risk & Speed Time-toMarket
Receive Prototypes
Send Prototypes to Customer
Approve Prototypes
Begin Volume Production
Customer
Altera
Note:
1 If placement constraints are provided, then Altera will place
as per these constraints and only route the design.
Altera builds HardCopy devices based on customerprovided in-system-verified FPGA design files and
constraints. From these source files, Altera preserves
Figure 3. Implementation Timeline
Migration &
Verification
Custom Mask Prototype
Fabrication Assembly & Test
Prototype
Approval
Production
2 Weeks
5 to 7 Weeks
3 Weeks
8 Weeks
18 to 20 Weeks
4
Altera Corporation
Design HardCopy Devices with the
Quartus II Software
Altera’s Quartus® II software is the industry’s only
design tool to offer a unified flow for designing
FPGAs and HardCopy devices. For the first time,
designers using the Quartus II software (version 3.0
and later) can target a HardCopy Stratix device
upfront, using similar design flow, architecture, and
tools as for a Stratix™ FPGA. The option to estimate
post-migration performance and power consumption
and optimize the HardCopy device gives system
architects the ability to design their systems for
maximum throughput (see Figure 4).
Table 1 highlights some of the features in the
Quartus II software that support HardCopy device
design. The Quartus II design software supports all
HardCopy Stratix, HardCopy APEX 20KC, and
HardCopy APEX 20KE devices. For a complete
description of the Quartus II design software
features, visit the Altera web site (www.altera.com).
Figure 4. Performance & Power Consumption with the Quartus II Software
• Rapid Design Changes
• Flexible Quantities
• In-System Verification
• Seamless Migration
• Minimal Risk, Low Cost
• Performance & Power Benefits
• Guaranteed First-Silicon Success
• Performance & Power Estimation
• HardCopy Floorplans
• Design Optimization
• System Design for Maximum
Throughput
Stratix FPGA
HardCopy Stratix
Device
Proven Netlist,
Pin Assignments
& Timing Constraints
Proven Netlist,
New Timing &
Placement Constraints
HardCopy Placement
& Timing Analysis
Yes
Timing
Met?
No
70% Reduction
in Die Size
Table 1. HardCopy Migration Features in the Quartus II Software
DESCRIPTION
FEATURE
HardCopy Floorplans and Timing Models1
Targets designs to HardCopy Stratix devices and facilitates estimation of device
performance and power consumption. Allows designers to view the actual
placement of their design in the floorplan.
HardCopy Timing Optimization Wizard1
Provides the ability to estimate performance and lower power consumption of
the design and optimize design to meet requisite specifications.
Design Assistant
Ensures that the design is compliant with HardCopy design rules to facilitate a
smooth migration.
HardCopy Files Wizard
Assembles all the required deliverables for migration to a HardCopy device.
HARDCOPY_FPGA_PROTOTYPE Device
Allows designers to verify their designs in an FPGA and ensure that the design
can be smoothly migrated to a HardCopy device.
HardCopy Stratix Power Calculator
This allows the designer to estimate power consumption without using
simulation vectors. The calculator is also available on the Altera web site.
Note:
1 This feature is for use with HardCopy Stratix devices only.
Altera Corporation
5
State-of-the-Art Devices
HardCopy Stratix Devices
The HardCopy device family includes HardCopy Stratix,
HardCopy APEX 20KE, and HardCopy APEX 20KC
devices. Each of the HardCopy devices employ the same
high-density architecture as the corresponding FPGA
and are available in space-saving FineLine BGA®
packages.
HardCopy devices support powerful system-level
device features, such as:
■
Packaging: HardCopy devices are available in the
same packages with the same pin-outs as the
corresponding FPGA, maintaining pin-compatibility.
■
Built-in testability: All HardCopy devices include
embedded test circuits. Altera automatically
generates production test vectors with high fault
coverage and does not require any customergenerated test vectors.
■
IP: Migration of Altera MegaCore and Altera
Megafunction Partners Program (AMPPSM) functions.
Altera’s HardCopy Stratix devices retain the same
rich features as Stratix FPGAs, including the
0.13-µm all-layer-copper process, hierarchical clock
structure, TriMatrix™ memory, and highly optimized
embedded digital signal processing (DSP) blocks.
HardCopy Stratix devices support a wide range of
high-speed interfaces—including SPI-4 Phase 2,
10-Gigabit Ethernet (XSBI), and the RapidIO™
standard—as well as a variety of high-speed I/O
standards including the LVDS, LVPECL, and
HyperTransport™ standards. These advanced
capabilities allow designers to connect high-speed
memory devices like quad-data rate (QDR) and
zero-bus turnaround (ZBT) SRAMs.
The HardCopy Stratix devices are perfect for highperformance, high-volume applications in the
networking, wireless communication, high-end
consumer electronics, industrial, test, and medical
markets. Table 2 shows the features and packages
available with HardCopy Stratix devices.
Table 2. HardCopy Stratix Device Overview
FEATURE
HC1S25
HC1S30
HC1S40
HC1S60
HC1S80
Logic Elements (LEs)
25,660
32,470
41,250
57,120
79,040
M512 RAM Blocks
(512 Bits + Parity)
224
295
384
574
767
M4K RAM Blocks
138
171
183
292
364
M-RAM Blocks1
2
21
21
6
61
Total RAM bits
1,944,576
2,137,536
2,244,096
5,215,104
5,658,048
DSP Blocks
10
12
14
18
22
Embedded Multipliers2
80
96
112
144
176
Phase-Locked Loops (PLLs)
6
6
6
12
12
473
597
615
773
773
672-pin
ball-grid array
(BGA)3
780-pin BGA
780-pin BGA
1,020-pin BGA
1,020-pin BGA
Maximum User I/O Pins
Packages
Notes:
1 The number of M-RAM blocks in this device differs from the number of M-RAM blocks in the corresponding Stratix FPGA device.
2 Total number of 99 multipliers. To obtain the total number of 1818 multipliers per device, divide the total number of 99
mutipliers by a factor of 2. To obtain the total number of 3636 multipliers per device, divide the total number of 99 multipliers by
a factor of 8.
3 Fine Line BGA package (1.0-mm pitch).
6
Altera Corporation
Contact Altera Today
HardCopy APEX 20KE &
HardCopy APEX 20KC Devices
HardCopy devices provide the best high-volume
solution for your high-density FPGA designs. Visit
the Altera web site today to learn more about
HardCopy devices.
HardCopy APEX 20KE and HardCopy APEX 20KC
devices represent the first-generation HardCopy
devices introduced by Altera. HardCopy APEX 20KE
and HardCopy APEX 20KC devices maintain the
equivalent APEX™ 20KC and APEX 20KE FPGA
architecture and their features. Table 3 shows
the features and packages available with
HardCopy APEX 20KE and HardCopy APEX 20KC
devices.
Table 3. HardCopy APEX 20KE & HardCopy APEX 20KC Device Overview
FEATURE
HC20K400
HC20K600
HC20K1000
HC20K15001
400,000
600,000
1,000,000
1,500,000
1,052,000
1,537,000
1,772,000
2,392,000
16,640
24,320
38,400
51,840
104
152
160
216
212,992
311,296
327,680
442,368
4
4
4
4
1,664
2,432
2,560
3,456
488
508
708
808
652-pin BGA,
672-pin BGA2
652-pin BGA
672-pin BGA2
652-pin BGA
672-pin BGA2
1,020-pin BGA2, 3
652-pin BGA
1,020-pin BGA2, 3
Typical Gates
Maximum System Gates
LEs
ESBs
Maximum RAM Bits
PLLs
Maximum Macrocells
Maximum User I/O Pins
Packages
Notes:
1 HardCopy APEX 20KE device only.
2 FineLine BGA package.
3 “F33” ordering code.
Altera Corporation
7
Altera Offices
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
USA
Telephone: (408) 544-7000
www.altera.com
Altera European Headquarters
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1 494 602 000
Altera Japan Ltd.
Shinjuku i-Land Tower 32F
6-5-1, Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
www.altera.com/japan
Altera International Ltd.
2102 Tower 6
The Gateway, Harbour City
9 Canton Road
Tsimshatsui Kowloon
Hong Kong
Telephone: (852) 2945 7000
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and
logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. RapidIO
is a trademark of the RapidIO Trade Association. HyperTransport is a trademark of the HyperTransport Consortium. All other product or service names are the property of their
respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
GB-HARDCOPY-2.2