Excalibur Remote
Reconfiguration
Demonstration Design
February 2003, ver. 1.0
Introduction
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Application Note 213
The Excalibur™ devices have a powerful embedded processor, which is
integrated with the APEX® FPGA. The embedded processor is active,
independent of the FPGA configuration, which allows software control of
the FPGA contents. The remote reconfiguration demonstration design is
an example of software control of the FPGA contents.
For more information on the Excalibur devices, refer to the Excalibur
Devices Hardware Reference Manual.
This application note discusses the following topics:
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Design
Overview
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Design Overview
Installing the design
Running the design
The remote reconfiguration demonstration design is a simple
implementation that uses a web server application to remotely
reconfigure the Excalibur device.
For details on the web sever demonstration design, refer to AN285:
Excalibur Web Server Demonstration.
The remote reconfiguration demonstration design can post data via a
TCP/IP connection to the web server and can select different images to
boot and run based on boot parameters.
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For more information, refer to AN298: Reconfiguring Excalibur Devices
Under Processor Control.
Figure 1 shows a block diagram of the remote reconfiguration
demonstration design.
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AN-213-1.0
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
Figure 1. Block Diagram
SDRAM
EPXA10 Development Board
SDRAM
Controller
RS-232
UART
EPXA10 Device
10/100
Ethernet MAC
Flash
10/100 PHY
Device
PC
RJ-45
The remote reconfiguration demonstration design consists of an Excalibur
EPXA10 development board, which acts as the web server. The EPXA10
development board interfaces to the host PC through an RS-232 that is
connected to the UART for status information. The RJ45 is connected to a
10/100 Ethernet MAC MegaCore® function for transmission control
protocol/internet protocol (TCP/IP) data. Webpages are stored in the
system and present an interface to upload new .hex files and reconfigure
the EPXA10 device with a new application.
Figure 2 shows the flow for the remote reconfiguration demonstration
design.
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
Figure 2. Flow Diagram
System Reset
System
Initialization and
Read Boot Flag
New Image
Initialization
Clear Boot Flag
Yes
Boot Flag Set?
No
Run Web Server
Receive New
.hex file
No
Yes
Run New
Application
Verify .hex and
convert .hex to
binary
Set Boot Flag
Reset System
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
The design initializes the EPXA10 device and reads the boot parameters.
The parameter read is a simple flag that is set in flash. If the boot flag is not
set, the web server application continues to boot. Once the web sever is up
and running, you can post a new .hex file to the web server. After the .hex
file is written and verified the boot flag is then set and the board is reset.
After reset, the EPXA10 device is initialized and the boot flag is read.
When the flag is determined to be set, the new image is branched to and
then executed. One of the first steps of the new image is to clear the boot
flag to boot the web server on reset.
Install the
Design
This sections details the hardware and software requirements and the
design directory structure.
Hardware & Software Requirements
The remote reconfiguration demonstration design requires the following
hardware and software:
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EPXA10 development board revision 2.1 (see readme.txt for details
on using the revision 3.0 board)
Quartus® II software version 2.2
ARM Developer Suite for Altera (Altera ADS-Lite) software
version 1.1
Altera 10/100 Ethernet MAC MegaCore® function version 1.3.0
OpenCore® Plus evaluation license
Terminal Program, e.g., Minicom or Hyperterminal
For an OpenCore Plus license, refer to
www.altera.com/support/licensing/ip/lic-ipm-ocp.jsp.
Directory Structure
To install the remote reconfiguration demonstration design, unzip
an213.zip into the installation directory of your choice.
Figure 3 shows the directory structure
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
Figure 3. Directory Structure
remote_reconfig
alu_demo
Contains the Quartus II project for the ALU demonstration design.
rtl
Contains RTL files for the ALU demonstration design.
software
Contains embedded software for the ALU demonstration design.
hello_world
Contains the Quartus II project for the hello world demonstration design.
software
Contains embedded software for the hello world demonstration design.
webserver
Contains the Quartus II project for the web server.
software
Contains the embedded software source for the design; this includes the source for the
plugs library.
inc
Contains project header files.
lib
Contains the plugs library and other functions used in the design.
web
Contains the web pages.
Run the Design
To run the remote reconfiguration demonstration design, perform the
following steps:
1.
“Compile the Embedded Software”
2.
“Configure the EPXA10 Development Board”
3.
“Setup the Host PC”
4.
“Download New Images”
Compile the Embedded Software
The design has the following default TCP/IP settings:
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Development board IP address: 137.57.193.114
Development board subnet mask: 255.255.255.0
Gateway address: 137.57.193.254
DNS address: 137.57.109.1
If the default settings remain unchanged, or if you are connecting to the
board directly with a crossover cable, proceed to “Configure the EPXA10
Development Board” on page 6.
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
If the default TCP/IP settings are not acceptable for your network,
perform an embedded software build. To build the embedded software,
perform the following steps.
1.
Change the IP address for the EPXA10 development board to the
desired settings by modifying the following lines in the
\software\web.c file:
settings.nameserver_ip_address = nm_ip2n(137,57,109,1);
settings.subnet_mask = nm_ip2n(255,255,255,0);
settings.gateway_ip_address = nm_ip2n(137,57,193,254);
settings.ip_address = nm_ip2n(137,57,193,168);
2.
Execute the \webserver\build_project.bat file.
Configure the EPXA10 Development Board
You must configure the EPXA10 Development board to work with this
design. To setup the jumpers and connect the development board to the
host PC and network, perform the following steps:
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
1.
To configure the EPXA10 development board to boot from flash and
enable the 78Q2120 Ethernet PHY device MII clocks to the EPXA10
device, adjust the jumper settings. Table 1 shows the jumper settings.
Table 1. Jumper Settings
Jumper
JP1
On
JP2
Connect 2 to 3
JP3
Connect 2 to 3
JP4
Connect 2 to 3
JP5
Connect 2 to 3
JP6
Connect 2 to 3
JP14
Off
JP15
Off
JP16
Off
JP17
Off
JP18
Off
MSEL0
Connect 1 to 2
MSEL1
Connect 1 to 2
JP31
Off
JP32
Off
JP33
Off
JSELECT
Connect 1 to 2
DEBUG_EN
Connect 2 to 3
BOOT_FLASH
Connect 2 to 3
EN_SELECT
Off
JP40
Connect 2 to 3
JP41
Connect 2 to 3
U179
Connect 2 to 3
JP50
Connect 2 to 3
JP51
Connect 2 to 3
JP52
Connect 2 to 3
JP53
Connect 2 to 3
JP54
Connect 2 to 3
JP55
Connect 2 to 3
JP57
Off
JP58
3V3
JP59
JP_AGND2GND
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Setting
3V3
Connect 1 to 2
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
2.
Connect a straight-through Ethernet cable from the EPXA10 board to
a network hub. Alternatively, you can use a crossover Ethernet cable
to connect the EPXA10 board directly to your host PC.
3.
Connect a ByteblasterMV™ cable from your PC’s parallel port to the
MasterBlaster™ header on the EPXA10 development board.
4.
Connect null modem cable to the RS-232 P2 port (the one in the
upper left hand corner) on the EPXA10 development board.
Setup the Host PC
The reconfiguration demonstration design must communicate with a host
PC, for flash programming, to display debug information, and serve web
pages. To setup the host PC, perform the following steps:
1.
Start a terminal session with the following settings:
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38400 Baud
8 Data bits
No Parity
1 stop bit
No Flow control
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2.
In this design, the UART presents status information.
To download the combined FPGA and software image,
remote_reconfiguration_flash.hex, to the EPXA10 development
board flash, use the prog_hw.bat file.
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If you have not performed JTAG programming on the host
PC before, start the JTAG server by typing the following
command at a command prompt:
jtagconfig -add byteblastermv lpt1r
3.
Launch a web browser and enter the board IP address in the URL
field. For example http://137.57.193.168
Download New Images
The reconfiguration web page (see ) give you the ability to download new
images to the webserver.
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
Figure 4. Reconfiguration Web Page
The remote reconfiguration demonstration design has the following two
images that you can download and run:
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\alu_demo\alu_demo_flash.hex
\hello_world\hello_flash.hex
The new images can be run from EBI1 and they also reset the boot flag.
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Summary
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For more information on multiple boot options, refer to AN187 Booting
Excalibur Devices.
The remote reconfiguration demonstration design shows a simple
implementation for remotely reconfiguring an Excalibur device. The
design uses concepts described in AN187 Booting Excalibur Devices to run
a second image that is downloaded to the device over a TCP/IP connect.
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AN 213: Excalibur Remote Reconfiguration Demonstration Design
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