POS-PHY Level 4—POS-PHY
Level 3 Bridge
Reference Design
October 2001; ver. 1.02
General
Description
Application Note 180
This application note describes how the POS-PHY Level 4—POS-PHY
Level 3 Bridge reference design can be used to bridge packet or cell traffic
from a single OC-192c SONET/SDH stream (single-PHY) to four OC-48
network processors, in ingress and egress directions. Figure 1 shows an
example block diagram. For quad-OC-48c line card applications, this
reference design is not required and the multi-PHY POS-PHY Level 4
MegaCore function could be connected directly to the POS-PHY Level 3
MegaCore functions.
Figure 1. Typical Application
POS-PHY Level 3 interfaces
Ingress
Network
POS-PHY Level 4 interface
Processor
(OC-48)
Network
Processor
POS-PHY Level 4
OC-192c
Framer
(OC-48)
to
POS-PHY Level 3
Bridge
Network
Processor
(OC-48)
Network
Processor
APEX II device
(OC-48)
Egress
Altera Corporation
A-AN-180-1.02
1
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Features
■
■
■
■
■
■
Provides an interface between the Altera® POS-PHY Level 4 and POSPHY Level 3 MegaCore® functions
Provides round-robin distributional packets from the POS-PHY
Level 4 interface to the POS-PHY Level 3 interfaces, feedback is based
on buffer fill levels
Supports up to four POS-PHY Level 3 functions, and one POS-PHY
Level 4 function, all configured for single-PHY mode
Supports POS-PHY Level 4 data rates of up to 13.312 gigabits per
second (Gbps)
Supports POS-PHY Level 3 data rates of up to 3.328 Gbps
Uses the AtlanticTM interface for ingress and egress directions
POS-PHY Level 4 and Level 3 MegaCore Functions
The POS-PHY Level 4 and POS-PHY Level 3 MegaCore functions support
packet transfers between physical (PHY) and link layer devices. They
support single-PHY (SPHY) or multi-PHY (MPHY) operation. This
reference design is for single-PHY applications only.
The POS-PHY Level 4 MegaCore function supports a data rate of up to
13.312 Gbps (832 MHz x 16 bits).
The POS-PHY Level 3 MegaCore function has a data rate of up to 3.328
Gbps (104 MHz x 32 bits).
When the POS-PHY Level 4 function has a data rate of 9.952 Gbps, it can
be connected to three (9.952 Gbps /3.328 Gbps) POS-PHY Level 3
functions. This is known as “minimum case”.
When the POS-PHY Level 4 function has a data rate of 13.312 Gbps, it can
be connected to four (13.312 Gbps / 3.328 Gbps) POS-PHY Level 3
functions. This is known as “maximum case”.
Atlantic Interface
The Atlantic interface is a full-duplex synchronous bus protocol
supporting both packets and cells. The Atlantic interface’s configurable
width of 8, 16, 32, 64, or 128 bits allows translation between different bus
types.
The POS-PHY Level 4 MegaCore function is an Atlantic interface slave
source and sink. It uses a 128-bit wide data path to deliver packets to the
POS-PHY Level 4—POS-PHY Level 3 bridge reference design which is
also an Atlantic interface slave source and sink.
2
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
The Atlantic interface provides a connection between the bridge and the
FIFO buffers. The width of the output bus (to FIFO buffer) is also 128-bits
wide. The FIFO buffers are used for crossing the clock domain from the
Atlantic interface to the POS-PHY Level 3 MegaCore functions. The
Atlantic interface width from the FIFO buffers to the POS-PHY Level 3
MegaCore functions is 32 bits.
B
For further information on this interface, refer to the Atlantic Interface
Functional Specification, available at http://www.altera.com.
Packet Sizes
Packet sizes can vary, but the empty (MTY), start of packet (SOP) and
end of packet (EOP) signals must be functional.
Figure 2 shows a high-level block diagram of the POS-PHY Level 4 to
POS-PHY Level 3 reference design, and neighboring functions.
Figure 2. Ingress Block Diagram
Atlantic Interfaces
Data
FIFO
Control
FIFO
POS-PHY
Level 4
Control
POS-PHY Level 4
Control
(10,238 bytes)
Data
Control
Data
to
MegaCore
Function
(10,238 bytes)
Control
POS-PHY Level 3
Data
Reference Design
FIFO
Control
(10,238 bytes)
FIFO
Control
Altera Corporation
(10,238 bytes)
Control
Data
Control
Data
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
3
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Figure 3 shows a high-level block diagram of the POS-PHY Level 3 to
POS-PHY Level 4 reference design, and neighboring functions.
Figure 3. Egress Block Diagram
Atlantic Interfaces
Control
Data
Control
POS-PHY
Level 4
Control
MegaCore
Function
POS-PHY Level 3
Data
FIFO
(14,400 bytes)
FIFO
(14,400 bytes)
Control
Data
Control
Data
to
Data
POS-PHY Level 4
Reference Design
Control
Data
FIFO
(14,400 bytes)
Control
Data
Control
Control
FIFO
Data
Functional
Description
4
(14,400 bytes)
Data
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
POS-PHY
Level 3
PHY Interface
MegaCore
Function
This reference design comprises two bridges: one bridge connects a single
POS-PHY Level 4 source (receiver) to multiple POS-PHY Level 3 sinks
(transmitters), the other bridge connects multiple POS-PHY Level 3
sources to a single POS-PHY Level 4 sink.
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
POS-PHY Level 4 to POS-PHY Level 3 Bridge
Figure 4 shows a block diagram of a bridge with a single POS-PHY Level
4 source and multiple POS-PHY Level 3 sinks.
Features
■
■
■
■
■
Connects a slave source to multiple slave sinks by acting as a master
on both sides
Supports one POS-PHY Level 4 function on the source side, and up to
four POS-PHY Level 3 functions on the sink side
Supports POS-PHY Level 4 data rates of up to 13.312 Gbps
Supports POS-PHY Level 3 data rates of up to 3.328 Gbps
Uses the Atlantic interface in the source and sink directions
Figure 4. POS-PHY Level 4 to POS-PHY Level 3 Bridge.
snkdat[127:0]
snksop
snkeop
snkmty[3:0]
To all
POS-PHY
Level 3
MegaCore
Functions
snkerr
srcdat[127:0]
srcdav
POS-PHY Level 4
From
srcval
to
POS-PHY
srcsop
POS-PHY Level 3
srceop
Bridge
Level 4
MegaCore
srcmty[3:0]
snk1ena
snk1dav
snk2ena
snk2dav
Function
POS-PHY
Level 3
MegaCore
Function #1
POS-PHY
Level 3
MegaCore
Function #2
srcerr
srcena
snk3ena
snk3dav
snk4ena
snk4dav
Altera Corporation
POS-PHY
Level 3
MegaCore
Function #3
POS-PHY
Level 3
MegaCore
Function #4
5
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
The POS-PHY Level 4 to POS-PHY Level 3 bridge monitors srcdav from
the POS-PHY Level 4 MegaCore function. When the POS-PHY Level 4
function has enough data to send a complete packet, it asserts its srcdav.
When srcdav is asserted, the bridge polls the four POS-PHY Level 3
functions in a round robin fashion, searching for an asserted data
available signal—snkndav—(where n can be 1, 2, 3, or 4). The bridge
connects the first POS-PHY Level 3 function with an asserted dav line to
the POS-PHY Level 4 function which begins the packet transfer. This
transfer occurs until srceop is asserted, indicating that a complete packet
has been sent. The bridge can now repeat the polling cycle.
POS-PHY Level 3 to POS-PHY Level 4 Bridge
Figure 5 shows a block diagram of a bridge with multiple POS-PHY Level
3 sources and a single POS-PHY Level 4 sink.
Features
■
■
■
■
■
6
Connects multiple slave sources to a slave sink by acting as a master
on both sides
Supports up to four POS-PHY Level 3 functions on the source side,
and one POS-PHY Level 4 function on the sink side
Supports POS-PHY Level 4 data rates of up to 13.312 Gbps (clock rate
of 104 MHz)
Supports POS-PHY Level 3 data rates of up to 3.328 Gbps (clock rate
of 104 MHz)
Uses the Atlantic interface in the source and sink directions
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Figure 5. POS-PHY Level 3 to POS-PHY Level 4 Bridge
src1dat[127:0]
src1dav
src1val
From
POS-PHY
Level 3
MegaCore
Function #1
src1sop
src1eop
snkdat[127:0]
src1mty[3:0]
snkdav
src1err
src1ena
snksop
POS-PHY Level 3
to
snkeop
POS-PHY Level 4
Bridge
POS-PHY
Level 4
MegaCore
Function
snkmty[3:0]
src4dat[127:0]
src4dav
src4val
From
POS-PHY
Level 3
MegaCore
Function #4
snkerr
snkena
src4sop
src4eop
src4mty[3:0]
src4err
src4ena
The POS-PHY Level 3 to POS-PHY Level 4 bridge monitors snkdav from
the POS-PHY Level 4 MegaCore function. When the POS-PHY Level 4
function has enough space to accept a complete packet, the snkdav signal
is asserted. When snkdav is asserted, the bridge polls the four POS-PHY
Level 3 functions in a round robin fashion, searching for the next one with
an asserted data available signal—srcndav—(where n can be 1, 2, 3, or
4). The bridge connects the output signals from the first POS-PHY Level 3
function with an asserted dav line to the POS-PHY Level 4 input signals
for packet transfer. The transfer occurs until the srceop signal is asserted,
indicating that a complete packet has been sent. The bridge can now
repeat the polling cycle.
Altera Corporation
7
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
FIFO Buffer
Size
Packet sizes can vary from 1 byte to 9600 bytes.
This section calculates the FIFO buffer sizes needed based on the limits set
by the minimum and maximum cases, see “POS-PHY Level 4 and Level 3
MegaCore Functions” on page 2.
POS-PHY Level 4 to POS-PHY Level 3
Data Rate Relationship is 3DPL3 = DPL4 using 3 FIFO Buffers
Data is sent out of the FIFO buffer at 1/3 of the rate at which it is received.
Therefore, in the period that a packet of 9,600 bytes is received, 3,200 bytes
have been sent out leaving 6,400 bytes in the FIFO buffer.
In the worst-case scenario, the FIFO buffers receive the following number
of bytes, in order:
FIFO buffer 1 receives 9,600 bytes
FIFO buffer 2 receives 6,400 (2/3 of 9,600) bytes
FIFO buffer 3 receives 4,267 (2/3 of 6,400) bytes
While the latter FIFO buffers are still receiving data, the former
FIFO buffers are constantly sending out data.
By the time the third FIFO buffer has received the complete packet of 4,267
bytes, all three FIFO buffers contain 2,844 (2/3 of 4,267) bytes. If the next
packet received is 9,600, the FIFO buffer will contain 2,844 + (2/3 of 9,600)
= 9,245 bytes.
Therefore, the maximum size of each of the four FIFO buffers should be
9,245 bytes.
8
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Formula:
D - Relationship between the rate of reading out of, and the rate of writing
into the FIFO buffer.
D =
D ata rate o f re ad in g, P L3 rate
D ata rate o f w ritin g, P L4 ra te
PL3 rate < PL4 rate, therefore D < 1.
F – Number of FIFO buffers
P – Maximum packet size (in bytes)
Fs – Minimum FIFO buffer size needed
F s = (1- D ) F xP + (1-D )xP
T = (1 - D) × P
This formula can be used only if F > 1/D.
Example 1:
If D = 1/3, F = 4, P = 9,600;
4
Minimum size of FIFO buffer needed, Fs = (2/3) x 9,600 + (2/3) x 9,600 =
8,296 bytes
Example 2:
If D = 1/4, F = 4, P = 9,600;
Minimum size of FIFO buffer needed, Fs = (3/4)4 × 9,600 + (3/4) × 9,600 =
10,238 bytes
Altera Corporation
9
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
POS-PHY Level 3 to POS-PHY Level 4
Formula:
D - Relationship between the rate of reading out of, and the rate of writing
into the FIFO buffer.
D =
D ata rate o f w ritin g, P L3 ra te
D ata rate o f re ad in g, P L4 rate
PL3 rate < PL4 rate, therefore D< 1.
F – Number of FIFO buffers
P – Maximum packet size (in bytes)
Fs – Minimum FIFO buffer size needed
T– Lower Threshold, the number of bytes needed in the FIFO buffer
before the packet can be read
(F – 1)
Fs = 2 ----------------- xP
F
T = ( 1 – D )xP
Data Rate Relationship is 3DPL3 = DPL4 using 3 FIFO Buffers
Data is sent out of the FIFO buffer at three times the rate at which it is
received. Therefore, in the period that a packet of 9,600 bytes is read, 3,200
bytes have been written. Each FIFO buffer asserts its data available (dav)
signal when the lower threshold (T) value has been reached, or an EOP
signal has been written into the FIFO buffer.
10
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Table 1 shows the data flow within the three FIFO buffers.
Table 1. Data Flow (3 FIFO Buffers)
Time
Action
Bytes Contained in each FIFO Buffer
FIFO 0
FIFO 1
FIFO 2
0
Start
0
0
0
1
FIFO buffers 0, 1, and 2 write in 3,200 bytes.
3,200
3,200
3,200
2
FIFO buffers 0, 1, and 2 write in another 3,200 bytes.
6,400
6,400
6,400
3
9,600 bytes from FIFO buffer 0 are read out.
FIFO buffers 0, 1, and 2 write in another 3,200 bytes.
0
9,600
9,600
4
9,600 bytes from FIFO buffer 1 are read out.
FIFO buffers 0, 1, and 2 write in another 3,200 bytes.
3,200
3,200
12,800
5
9,600 bytes from FIFO buffer 2 are read out.
FIFO buffers 0, 1, and 2 write in another 3,200 bytes.
6,400
6,400
6,400
6
9,600 bytes from FIFO buffer 0 are read out.
FIFO buffers 0, 1, and 2 write in another 3,200 bytes.
0
9,600
9,600
7
Repeat actions from Time 4 to Time 6.
The lower threshold (T) and the maximum FIFO buffer size are calculated
as follows:
Example:
If D = 1/3, F = 3, P = 9,600;
Minimum size of FIFO buffer needed, Fs = 2(3-1)/3 x 9,600 = 12,800 bytes
Lower Threshold, T = (2/3) × 9,600 = 6,400 bytes
Data Rate Relationship is 4DPL3 = DPL4 using 4 FIFO Buffers
Data is sent out of the FIFO buffer at four times the rate at which it is
received. Therefore, in the period that a packet of 9,600 bytes is read, 2,400
bytes have been written. Each FIFO buffer asserts its data available (dav)
signal when the lower threshold (T) value has been reached, or an EOP
signal has been written into the FIFO buffer.
Altera Corporation
11
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Table 2 shows the data flow within the four FIFO buffers.
Table 2. Data Flow (4 FIFO buffers)
Time
Action
Bytes Contained in each FIFO Buffer
FIFO 0
FIFO 1
FIFO 2
FIFO 3
0
Start
0
0
0
0
1
FIFO buffers 0, 1, 2 and 3 write in 2,400 bytes.
2,400
2,400
2,400
2,400
2
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
4,800
4,800
4,800
4,800
3
9,600 bytes from FIFO buffer 0 are read out.
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
7,200
7,200
7,200
7,200
4
9,600 bytes from FIFO buffer 1 are read out.
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
0
9,600
9,600
9,600
5
9,600 bytes from FIFO buffer 2 are read out.
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
2,400
2,400
12,000
12,000
6
9,600 bytes from FIFO buffer 3 are read out.
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
4,800
4,800
4,800
14,400
7
9,600 bytes from FIFO buffer 0 are read out.
FIFO buffers 0, 1, 2 and 3 write in another 2,400 bytes.
7,200
7,200
7,200
7,200
8
Repeat actions from Time 4 to Time 7.
The lower threshold (T) and the maximum FIFO buffer size are calculated
as follows:
Example:
If D = 1/4, F = 4, P = 9,600;
Minimum size of FIFO buffer needed, Fs = 2(4-1)/4 x 9,600 = 14,400 bytes
Lower Threshold, T = (3/4) × 9,600 = 7,200 bytes
I/O Signals
This table shows the generic signal names used for both the POS-PHY
Level 3 to POS-PHY Level 4 and the POS-PHY Level 4 to POS-PHY Level
3 blocks.
Table 3. I/O Signals (Part 1 of 2)
Signal (1)
Direction
Description
srcndat[127:0]
Input
Source data bus
srcndav
Input
Source data available (asserted when a complete packet of data is
available for transfer)
srcnsop
Input
Source start of packet
12
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Table 3. I/O Signals (Part 2 of 2)
srcneop
Input
Source end of packet
srcnmty [3:0]
Input
Source number of empty bytes
srcnerr
Input
Source error signal
srcnval
Input
Source valid data signal
srcnena
Output
Source enable signal
snkndat [127:0]
Output
Sink data bus
snkndav
Input
Sink data available (asserted when there is enough space to
receive a complete packet of data)
snknsop
Output
Sink start of packet
snkneop
Output
Sink end of packet
snknmty [3:0]
Output
Sink number of empty bytes
snknerr
Output
Sink error signal
snknena
Output
Sink enable signal
Note:
(1)
When there are multiple sources or multiple sinks, replace the n with the module number. If there is only one source
or sink, simply delete the n.
Configuration
The POS-PHY Level 4 to POS-PHY Level 3 Bridge reference design
supports almost all configurations of the POS-PHY Level 4 and POS-PHY
Level 3 MegaCore functions, provided both functions are configured for
single-PHY operation. Table 4 and Table 5 show example settings
required for the MegaCore functions to operate with the bridge.
Table 4. POS-PHY Level 4 MegaCore Function Configuration Settings (Part 1 of 2)
Optional Features
Choices
Data Flow Direction
Rx
Tx
Atlantic Data Width
128
128
Calender_ Length
1
1
No
No
Embedded Address (1)
FIFO Buffer Depth
256
256
FIFO Pipeline
30
30
Almost Empty
200
200
Almost Full
10
10
FIFO_Threshold Low
61
61
FIFO_Threshold High
50
50
Calender_M
2,048
2,048
Maxburst 1
1
1
Altera Corporation
13
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Table 4. POS-PHY Level 4 MegaCore Function Configuration Settings (Part 2 of 2)
Optional Features
Choices
Maxburst 2
MaxT
Training Pattern Repetitions
Transmit Bandwidth Optimization
5
5
251
251
No
No
Yes
Yes
Note:
(1)
The POS-PHY Level 4 MegaCore function must have its embedded address (EADDR) parameter set to No. The Yes
option is not supported in this bridge reference design.
Table 5. POS-PHY Level 3 MegaCore Function Configuration Settings
Optional Features
Parameters
Architecture Options
Interface A Bus Direction
Number of Channels
Source
1
Sink
1
Interface Type
A Interface
B Interfaces—Interface Type
POS-PHY Level 3
Link Layer
Atlantic Master
POS-PHY Level 3
Link Layer
Atlantic Master
Interface Settings
A Interface—Bus Width
32
32
B Interfaces—
Bus Width
Clock Selection
32
32
A Clock (No FIFO) A Clock (No FIFO)
Parity Settings
A Interface
B Interfaces—Parity Control
None
None
None
None
FIFO Settings
A Interface—
Empty Threshold
Burst
Remote Burst
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
B Interfaces—
Size
Full Threshold
Burst
Remote Burst
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Address & Packet
Available Settings
14
A Interface—Packet Available Mode
Choices
Direct
(No Addressing)
B Interfaces—Packet Available Mode Direct
(No Addressing)
Direct
(No Addressing)
Direct
(No Addressing)
Altera Corporation
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Resource
Usage
Table 6 lists the estimated resources used by the reference design and the
POS-PHY Level 4 and POS-PHY Level 3 MegaCore functions instantiated
to operate with the bridge. These numbers are subject to change
depending on the chosen configurations of the MegaCore functions.
Table 6. Resource Usage
POS-PHY Level 4 to POS-PHY Level 3 bridge
POS-PHY Level 3 to POS-PHY Level 4 bridge
LE
ESB
308
0
471
0
Atlantic FIFO from 32 bits to 128 bits (×4)
1,428(1)
36
Atlantic FIFO from 128 bits to 32 bits (×4)
1,192(2)
36
POS-PHY Level 4 MegaCore function Receiver
7,685
17
POS-PHY Level 4 MegaCore function Transmitter
3,227
17
POS-PHY Level 3 MegaCore function Receivers (×4)
612
0
POS-PHY Level 3 MegaCore function Transmitters (×4)
556
0
15,479
106
Total Resource Usage
Notes:
(1)
(2)
For the POS-PHY Level 3 to POS-PHY Level 4 bridge, the minimum FIFO buffer size needed for data is 14,400 bytes
(113 by 128-bit words).
For the POS-PHY Level 4 to POS-PHY Level 3 bridge, the minimum FIFO buffer size needed for data is 10,238 bytes
(80 by 128-bit words).
Altera Corporation
15
POS-PHY Level 4--POS-PHY Level 3 Bridge Reference Design Application Note
Timing
Figure 6 shows the timing relationship between the various I/O signals.
Figure 6. Timing Diagram
clock
srcdav
srcena
srcval
pk t n
srcdat,srcmty,srcerr
invalid
pk t n+1
D2
D3
Deop
Dsop
invalid
D2
D3
Dsop
D2
srcsop
srceop
Dsop (Pkt n)
internal sop buffer
Dsop (Pkt n+1)
snkdav
snkena
snkdat,snkmty,snkerr
invalid
Dsop
D2
D3
Deop
invalid
snksop
snkeop
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