®
May 2003, ver. 2.0
Synplify and Quartus II
LogicLock Design Flow
Application Note 165
Introduction
TM
The LogicLockTM block-based design flow enables users to design,
optimize, and lock down a design one section at a time. With the
LogicLock methodology, you can independently create and implement
each logic module into a hierarchical or team-based design. With this
method, you can preserve the performance of each module during system
integration and have more control over placement of your design. To
maximize the benefits of the LogicLock design methodology in the
Altera® Quartus® II software, you can partition a design into a hierarchy
of netlist files during synthesis in the Synplify software.
The LogicLock design methodology supports CycloneTM, StratixTM,
Stratix-GX, APEXTM II, APEX 20KC, APEX 20KE, APEX 20K, MercuryTM
(limited support), and ExcaliburTM devices. This application note
describes how to create and utilize multiple Verilog Quartus Mapping
(.vqm) netlist files for a hierarchical and incremental design approach
using the MultiPoint synthesis feature in the Synplicity Synplify software.
f
Software
Requirements
For more information on LogicLock regions and the LogicLock design
flow, see AN 161: Using the LogicLock Methodology in the Quartus II Design
Software.
This application note assumes that you have installed and licensed the
Synplify software. To get the Synplify software and license, go to the
Synplicity web site www.synplicity.com.
1
Design
Hierarchy
Altera Corporation
AN-165-2.0
The MultiPoint synthesis feature was introduced in the Synplify
Pro software version 7.2. The feature is not available in the basic
Synplify software.
As a part of your design hierarchy, you can define different modules in
different files and instantiate them in a top-level file. For larger designs,
such as those used for Stratix devices, a group of designers can work on
different modules of a design at the same time. Figure 1 shows an example
of a design hierarchy.
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Figure 1. Design Hierarchy
Designer 1
A
B
D
Designer 2
C
E
F
Designer 3
In Figure 1, the top-level design A is assigned to one engineer
(Designer 1), while two engineers work on the lower levels of the design.
Designer 2 works on B and its submodules D and E, while Designer 3
works on C and its submodule F.
You can treat each module or a group of modules as one block of the
design for incremental synthesis. Each block of submodules will have its
own netlist file after synthesis. A submodule can be a Verilog HDL
module, a VHDL entity, an VQM netlist file, or any combination of the
three. To combine these submodules into a block for synthesis, they
should form a single tree in the design. For example, you cannot create
one netlist file for the two submodules E and C while A and B are in
different netlists because E and C are in different trees or branches of the
design. You can have individual netlists for A, B, C, and E or one netlist
for the whole tree under the top-level design A.
LogicLock
2
With a hierarchical approach, the LogicLock design methodology allows
you to individually optimize your block(s) for the Altera device. Using the
LogicLock design methodology, you can place each block’s logic into a
fixed or floating region in an Altera device. You then have the opportunity
to maintain the placement and the performance of your blocks in the
Altera device.
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Using the LogicLock Design Flow with Synplify MultiPoint
Synthesis
The MultiPoint synthesis feature in the Synplify software allows you to
create different netlist files for different sections of a design hierarchy.
Different netlist files mean that each section is independent of the others.
When synthesizing the entire project, only portions of a design that have
been updated have to be re-synthesized when you compile the design.
You can make changes, optimize and re-synthesize your section of a
design without affecting other sections.
You can place each netlist file into a separate LogicLock region in the
Quartus II software. If a design region changes, only the netlist associated
with the changed region is affected. During place-and-route in the
Quartus II software, you only need to recompile the LogicLock region
associated with the changed netlist file. You may need to remove previous
back-annotated assignments for the modified block because the node
names may be different in the newly synthesized version.
If all the netlists are contained in one Quartus II project, use the LogicLock
flow to back-annotate the logic within the other regions. In this case, when
you recompile with one new VQM netlist file, the placement and
assignments for unchanged netlist files assigned to different LogicLock
regions are not affected. Therefore, one designer can make changes to a
piece of code that exists in an independent block and not interfere with
another designer’s changes, even if all the blocks are integrated in a toplevel design. With the LogicLock design methodology, separate pieces of
a design can evolve from development to testing without affecting other
areas of a design.
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For more information on the LogicLock incremental design capabilities,
refer to AN 161: Using the LogicLock Methodology in the Quartus II Design
Software.
Hierarchy & Design Considerations
You must plan your design’s structure and partitioning carefully to use
the LogicLock features effectively. Optimal hierarchical design practices
include partitioning the blocks at functional boundaries, registering the
boundaries of different blocks, minimizing the I/O between each block,
separating timing-critical blocks, and keeping the critical path within one
hierarchical block.
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For more tips on design planning, refer to AN 226: Synplify & Quartus II
Design Methodology.
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To ensure the proper functioning of the synthesis flow, you can only apply
the LogicLock option in the Synplify software to modules, entities, or
netlist files. In addition, each module or entity should have its own design
file. If two different modules are in the same design file but are defined as
being part of different regions, it is difficult to maintain incremental
synthesis since both regions would have to be recompiled when you
change one of the modules or entities.
If you use boundary tri-states in a lower-level block, the Synplify software
pushes (or “bubbles”) the tri-states through the hierarchy to the top level
because Altera devices only have tri-state drivers on output pins (not
internally). Because bubbling tri-states requires optimizing through
hierarchies, lower-level tri-states are not supported with a block-based
design methodology. You should use tri-state drivers only at the external
output pins of the device and at the top-level block in the hierarchy.
Creating a
Design with
Multiple VQM
Files
The first stage of a hierarchical design flow is to generate multiple VQM
files, enabling you to take advantage of the LogicLock incremental design
flow in the Quartus II software. If the whole design is in one VQM file,
changes in one block affect other blocks because of possible node name
changes.
You can generate multiple VQM files either by using the Multipoint
synthesis flow and LogicLock attributes in the Synplify software, or by
manually creating separate Synplify projects and black-boxing each block
that you want to be part of a LogicLock region. Once you have created
multiple VQM files using one of these two methods, you need to create
the appropriate Quartus II project(s) to place-and-route the design.
Generating a Design with Multiple VQM Files Using MultiPoint
Synthesis
This section describes how to generate multiple VQM files using the
Synplify Pro MultiPoint synthesis flow. You must first set up your
compile points, constraint files, and Synplify options, then apply
Altera-specific attributes to create LogicLock regions.
MultiPoint synthesis, which is available for certain device technologies in
the SynplifyPro software, provides an automated incremental synthesis
flow and can reduce runtime. The Synplicity MultiPoint synthesis flow
lets you design incrementally and synthesize designs that take too long
for top-down synthesis.
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The MultiPoint feature manages a design hierarchy for incremental
synthesis. MultiPoint synthesis allows different netlist files to be created
for different sections of a design hierarchy, supporting the LogicLock
design methodology. It also ensures that only those sections of a design
that have been updated will be re-synthesized when the design is
compiled, reducing synthesis run time and preserving the results for the
unchanged blocks. A designer can change and re-synthesize their section
of a design without affecting other sections of a design.
Step 1. Set Compile Points and Create Constraint Files
The MultiPoint flow lets you segment a design into smaller synthesis
units, called compile points. The synthesis software treats each compile
point as a block for incremental mapping, which allows you to isolate and
work on individual compile point modules as independent segments of
the larger design without impacting other design modules. A design can
have any number of compile points, and compile points can be nested.
The top-level module is always treated as a compile point.
Compile points are optimized in isolation from their parent which could
be another compile-point or a top-level design. Each block created with a
compile point is unaffected by critical paths or constraints on its parent or
other blocks. A compile point stands on its own, with its own individual
constraints. During synthesis, any compile points that have not yet been
synthesized are synthesized before the top level. Nested compile points
are synthesized before the parent compile points that contain them. When
you apply the appropriate LogicLock constraints to a compile point
module, then a separate netlist will be written for that compile point,
isolating that logic from any other logic in the design.
Compile points are applied to the module or architecture in the Synplify
Pro SCOPE spreadsheet or the constraint file (.sdc). You cannot set a
compile point in the Verilog/VHDL source code. You can set the
constraints manually using TCL or by editing the SDC file. You can also
use the graphical user interface (GUI) which provides two methods,
manual or automated as outlined below.
Defining Compile Points Using TCL or SDC
To set compile points using Tcl and .sdc, use the define_compile_point
command:
define_compile_point [-disable] [-comment <comment>]
<objname> [-type <compile point type>]
In the above syntax statement objname represents any module in the
design. Cyrrently, only locked compile point types are supported.
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Each compile point has a set of constraint files that begin with the
define_current_design command to set up the SCOPE
environment.
define_current_design {<my_module>}
Manually Defining Compile Points from the GUI
The manual method requires you to separately create constraint files for
the top-level and the lower-level compile points. To use the manual
method:
1.
From the top-level, select the Compile Points tab in the SCOPE
spreadsheet
2.
Select the modules which you want to define as compile points
types.
Currently, only locked compile points are supported. All compile points
must be defined from the top-level because the Compile Points tab is not
available in the SCOPE spreadsheet from lower level modules.
3.
Manually create a constraint file for each module.
To ensure that changes to a compile point do not affect the top-level
parent module, disable the Update Compile Point Timing Data option
on the Implementation Options dialog box. If this option is enabled,
updates to a child module can impact the top-level module.
Automatically Defining Compile Points from the GUI
When you use the automated process, the lower-level constraint file is set
up automatically. This eliminates the manual step that you need to do to
set up each compile point. To use the automated method:
6
1.
Select New under the File menu and choose to create a new
Constraint File, or click the SCOPE icon in the toolbar. Select
Compile Point from the Select File Type tab of the Create a New
SCOPE File dialog box.
2.
Select the module you want to designate as a compile point. The
software automatically sets the compile points in the top-level
constraint file and creates a lower-level constraint file for each
compile point.
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To ensure that changes to a compile point do not affect the top-level
parent module, disable the Update Compile Point Timing Data option
on the Implementation Options dialog box. If this option is enabled,
updates to a child module can impact the top-level module.
1
–
–
–
–
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When using compile points with the LogicLock design flow,
keep the following restrictions in mind:
To use compile points effectively, you must provide timing
constraints (timing budgeting) for each compile point; the more
accurate the constraints, the better your results. Constraints are
not automatically budgeted, so manual time budgeting is
essential.
When using the Synplify Pro attribute syn_useioff to pack
registers in the I/O Elements (IOEs) of Altera devices, these
registers must be in the top-level module, not a lower level.
Otherwise, you must use the Fast Input Register or Fast Output
Register options in the Quartus II software instead of the
syn_useioff attribute.
You must put tri-state buffers the top-level module because tristate drivers are located at the outputs of Altera devices. Tristates coded in lower-level files do not get automatically pushed
to the top-level.
There is no incremental synthesis support for top-level logic; any
logic in the top-level is re-synthesized every run.
For further details about compile points, see the Synplify Pro User Guide
and Reference Manual at
http://www.synplicity.com/literature/index.html.
Step 2. Apply the Altera LogicLock Attributes
To instruct the SynplifyPro software to create a separate VQM netlist file
for each compile point, you must indicate that the compile point will be
used with the LogicLock design methodology. When you apply the
appropriate LogicLock attributes, the SynplifyPro software will also write
out Tcl commands for the Quartus II software to create a LogicLock
region for each netlist.
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LogicLock regions in the Quartus II software have both size and location
properties. The region’s size is defined by the height and width of the
rectangular area. If the region is specified as auto-size, then the Quartus II
software determines the appropriate size to fit the logic assigned to the
region. When you specify the size, you must include enough device
resources to accommodate the assigned logic. The location of a region is
defined by its origin, the position of its top-left corner. In the Quartus II
software, this location can be specified as locked or floating. If the
location is floating, the Quartus II software determines the location during
its optimization process. Floating locations are the only type currently
supported in the SynplifyPro software.
Table 1 shows the valid combinations of the LogicLock location and size
properties in the SynplifyPro software:
Table 1. LogicLock Location and Size Properties
altera_logiclock_location altera_logiclock_size
Attribute
Attribute
Description
Floating
Auto
The most flexible kind
of LogicLock
constraint. Allows the
Quartus II software to
choose appropriate
region size and
location.
Floating
Fixed
Assumes size of
LogicLock constraint
area is already optimal
in existing Quartus II
project.
You can apply these attributes to the top-level constraint file or to the
individual constraint files for each lower-level module.
Synplify Pro offers another attribute, syn_allowed_resources, which
restricts the number of resources for a given module. You can apply a
syn_allowed_resources attribute to any compile point view.
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For specific information regarding these attributes, refer to the Synplify
Pro online help or Reference Manual.
During compilation, the Synplify Pro software creates a <top-level
project>.tcl file that provides the Quartus II software with the appropriate
LogicLock assignments, creating a region for each VQM file along with
the information to set up a Quartus II project.
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The Tcl file contains the following commands for each LogicLock region.
This example is for module A (instance u1) in the project named top where
the region name cpll_1 was selected by Synplify Pro for the compile point.
project add_assignment "top" "cpll_1" "" "" "LL_AUTO_SIZE" "ON"
project add_assignment "top" "cpll_1" "" "" "LL_STATE" "FLOATING"
project add_assignment "top" "cpll_1" "" "|A:u1" "LL_MEMBER_OF" "cpll_1"
These commands will create a LogicLock region with Auto Size and
Floating Origin properties. This flexible LogicLock region allows the
Quartus II Compiler to select the size and location of the region.
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For more information on Tcl commands, refer to AN 195: Scripting with Tcl
in the Quartus II Software.
Creating a Quartus II Project for Multiple VQM Files
You can use the following methods to import the VQM files into the
Quartus II software.
■
Use the <top-level project>.tcl file that contains the Synplify
assignments for all blocks within the project. This method allows the
top-level designer to import all the blocks into one Quartus II project
for an incremental flow. You can optimize all modules within the
project at once. Figure 2 shows a visual representation of the design
flow.
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If additional optimization is required for individual blocks,
each designer can take their VQM file and create a separate
Quartus II project at that time with the appropriate
assignments. New assignments would then have to be
added to the top-level project through the LogicLock import
function.
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Figure 2. Design Flow Using Multiple VQM Files with One Quartus II Project
Quartus II Project
a.vqm
Use a.tcl to Import
Synplify Pro Assignments
b.vqm
c.vqm
or
■
10
Generate multiple Quartus II projects, one for each block in the
design. Each designer in the project can optimize their block
separately within the Quartus II software and back-annotate their
blocks. Figure 3 shows a visual representation of the design flow. The
optimized sub-designs can be brought into one top-level Quartus II
project using the LogicLock import function. Each designer will have
to manually enter their assignments into the Quartus II software
because Synplify Pro doesn’t write a Tcl file for the lower-level
modules.
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Figure 3. Design Flow Using Multiple VQM Files with Multiple Quartus II Projects
Quartus II Project
a.vqm
Quartus II Project
b.vqm
Manually Enter
Assignments
f
Use a.tcl to Import
SynplifyPro Assignments
Quartus II Project
c.vqm
Manually Enter
Assignments
For more information on importing LogicLock assignments, refer to
AN161: Using the LogicLock Methodology in the Quartus II Design Software.
Generating a Design with Multiple VQM Files Using Black Boxes
This section describes how to manually generate multiple VQM files
using a black boxing technique. The following manual flow was
supported in previous versions of the SynplifyPro software, and is
discussed here because some designers or teams may want more control
over the project for each submodule. In addition, this manual flow is
supported in the Synplify (non-Pro) software that does not include the
Multipoint Synthesis feature.
Manually Creating Multiple VQM Files Using Black-Boxes
To create multiple VQM files manually in the Synplify software, create a
separate project for each module and top-level design that you want to
maintain as a separate VQM file. Implement black-box instantiations of
lower-level modules in your top-level project. When synthesizing the
projects for the lower-level modules and the top-level design, follow these
general guidelines.
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For lower-level modules:
1.
Turn on Disable I/O Insertion for the target technology in the
Implementation Options dialog box.
2.
Read the HDL files for the modules.
3.
Modules may include black-box instantiations of lower-level
modules that are also maintained as separate VQM files.
4.
Add constraints with the SCOPE constraint editor.
5.
Enter the clock frequency to ensure that the sub-design is correctly
optimized.
6.
In the Attributes tab, set syn_netlist_hierarchy to 0.
For top-level designs:
1.
Turn off Disable I/O Insertion for the target technology.
2.
Read the HDL files for top-level designs.
3.
Black-box lower-level modules in the top-level design.
4.
Add constraints with the SCOPE constraint editor.
5.
Enter the clock frequency to ensure that the design is correctly
optimized.
6.
In the Attributes tab, set syn_netlist_hierarchy to 0.
The sections below describe an example of black-boxing modules using
the files described in Figure 1 on page 2. To create multiple VQM files:
12
1.
Generate a VQM file for module C. Use C.v/.vhd and F. v/.vhd as the
source files.
2.
Generate a VQM file for module B. Use B.v/.vhd, D.v/.vhd, and
E.v/.vhd as the source files.
3.
Generate a top-level VQM file A.v/.vhd for module A. Ensure that
you black box modules B and C, which were optimized separately
in the previous steps.
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Black Boxing in Verilog HDL
Any design block that is not defined in the project, or included in the list
of files to be read for a project, will be treated as a black box by the
software. Use the syn_black_box attribute to indicate that you intended
to black-box the given module. In Verilog HDL, you must provide an
empty module declaration for the module that you will be treating as a
black box.
Figure 4 shows an example of the A.v top-level file. If any of your lowerlevel files also contain a black-boxed lower-level file in the next level of
hierarchy, follow the same procedure.
Figure 4. Black-Boxing Example for Top-Level File A.v
module A (data_in, clk, e, ld, data_out);
input data_in, clk, e, ld;
output [15:0] data_out;
wire [15:0] cnt_out;
B U1 (.data_in (data_in),.clk(clk), .ld (ld),.data_out(cnt_out));
C U2 (.d(cnt_out), .clk(clk), .e(e), .q(data_out));
// Any other code in A.v goes here.
endmodule
// Empty Module Declarations of Sub-Blocks B and C follow here.
// These module declarations (including ports) are required for black boxing.
module B (data_in, clk, ld, data_out) /*synthesis syn_black_box */ ;
input data_in, clk, ld;
output [15:0] data_out;
endmodule
module C (d, clk, e, q) /*synthesis syn_black_box */ ;
input [15:0] d;
input clk, e;
output [15:0] q;
endmodule
Black Boxing in VHDL
Any design block that is not defined in the project, or included in the list
of files to be read for a project, will be treated as a black box by the
software. Use the syn_black_box attribute to indicate that you intended
to black-box the given component. In VHDL, you need a component
declaration for the black box just like any other block in the design.
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1
Note that although VHDL is not case-sensitive, VQM (a subset
of Verilog) is case-sensitive. Entity names and their port
declarations are forwarded to the VQM. Black-box names and
port declarations are similarly forwarded to the VQM. To
prevent case-sensitive mismatches between VQM, use the same
capitalization for black-box and entity declarations in VHDL
designs.
Figure 5 shows an example of the A.vhd top-level file. If any of your
lower-level files also contain a black-boxed lower-level file in the next
level of hierarchy, follow the same procedure.
Figure 5. Black-Boxing Example for Top-Level File A.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY synplify;
use synplify.attributes.all;
ENTITY A IS
PORT ( data_in : IN INTEGER RANGE 0 TO 15;
clk, e, ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15
);
END A;
ARCHITECTURE a_arch OF A IS
COMPONENT B PORT(
data_in : IN INTEGER RANGE 0 TO 15;
clk, ld : IN STD_LOGIC;
d_out : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
COMPONENT C PORT(
d : IN INTEGER RANGE 0 TO 15;
clk, e: IN STD_LOGIC;
q : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
attribute syn_black_box of B: component is true;
attribute syn_black_box of C: component is true;
-- Other component declarations in A.vhd go here
signal cnt_out : INTEGER RANGE 0 TO 15;
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BEGIN
U1 : B
PORT MAP (
data_in => data_in,
clk => clk,
ld => ld,
d_out => cnt_out
);
U2 : C
PORT MAP (
d => cnt_out,
clk => clk,
e => e,
q => data_out
);
-- Any other code in A.vhd goes here
END a_arch;
After you have completed the steps outlined in this section, you will have
different VQM netlist files for each block of code. These files can now be
used in the LogicLock incremental design methodology in the Quartus II
software.
Creating a Quartus II Project for Multiple VQM Files
The Synplify software creates a Tcl file for each VQM file, providing the
Quartus II software with the information to set up a project. Altera
recommends the following method for bringing each VQM and
corresponding Tcl file into the Quartus II software:
Use the Tcl file that is created for each VQM file by the Synplify software
for each Synplify project. This method generates multiple Quartus II
projects, one for each block in the design. Each designer in the project can
optimize their block separately within the Quartus II software and backannotate their blocks. Figure 6 shows a visual representation of the design
flow. Designers should create a LogicLock region for each block; the toplevel designer should then import all the blocks and assignments into the
top-level project. This method allows each block in the design to be treated
separately; each block can be back-annotated and brought into one toplevel project.
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Figure 6. Design Flow Using Multiple Synplify Projects and Multiple Quartus II Projects
Quartus II Project
a.vqm
Quartus II Project
Use b.tcl to Import
Synplify Pro Assignments
f
Incremental
Synthesis Flow
b.vqm
Use a.tcl to Import
Synplify Pro Assignments
Quartus II Project
c.vqm
Use c.tcl to Import
Synplify Pro Assignments
For more information on creating and importing LogicLock regions, refer
to AN 161: Using the LogicLock Methodology in the Quartus II Design
Software.
Difference-Based Synthesis with the MultiPoint feature
When using the Multipoint synthesis flow, if you make changes to one or
more submodules, you can use incremental synthesis to generate a new
netlist for the changed submodule(s). The Multipoint flow within the
Synplify Pro software will use difference-based synthesis to regenerate
VQM files only for compile points that have been changed.
The Multipoint feature uses difference-based synthesis to maintain the
synthesis results for compile points that have not changed. Differencebased synthesis does not use time-stamp checks to see if a file has been
edited, it actually determines if any of the logic or constraints have
changed. This means that a module will not be re-compiled in the
MultiPoint flow if you add a comment or change the syntax – it will only
be re-compiled if the logic has changed.
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The Synplify synthesis process is divided into two parts: RTL
compilation and mapping. When using Multipoint synthesis, Synplify
Pro software stores an RTL netlist for each compile point after RTL
compilation (rtl.srd) and after mapping (mapped.srd). These
intermediate mapping files are located in a subdirectory named after the
compile point. In subsequent iterations of the design, the compiler reads
the current source code and the mapper will compare the new rtl.srd with
the old rtl.srd stored on the disk in the previous run. If these two RTL
netlists match then the mapper will not re-map that compile point, instead
it will use the stored mapped.rtl netlist. If the two RTL netlists differ then
the mapper will completely re-map this compile point. This flow is
referred to as difference-based synthesis.
A compile point that has already been synthesized is not resynthesized,
unless at least one of the following is true:
■
■
■
■
You change the HDL source code defining the compile point.
You change the constraints applied to the compile point.
You change any of the options on the Device panel of the ‘Options
for implementation’ dialog box (except Update Compile Point
Timing Data). In this case the entire design is resynthesized,
including all compile points.
You intentionally force the resynthesis of your entire design,
including all compile points, using the command Run ->
Resynthesize All.
1
Note that the intermediate mapping.srd files are used to save
mapping information for subsequent synthesis runs. If these files
are deleted, the associated compile point will be re-synthesized
and the files regenerated.
The Synplify Pro software does not currently propagate timing
constraints through hierarchical or nested compile points such that a child
compile point module inherits the .sdc file of a parent, or the compile
point module constraint file updates the constraint file of a parent. You
should add the correct timing model (time budgeting) for each constraint
file associated with each compile point module.
In the Quartus II software, use the LogicLock back-annotation feature to
lock down placement on modules that have not changed. When importing
a new VQM file you can keep the placement of the other logic in your
design and just update the new module.
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Altera Corporation
For more information on LogicLock back-annotation, refer to
AN 161: Using the LogicLock Methodology in the Quartus II Design Software.
17
AN 156: Using General-Purpose PLLs with APEX II Devices
Conclusion
The LogicLock incremental design flow uses module-based design to help
you preserve performance of modules and have control over placement.
By setting Synplify Pro compile points on the modules requiring separate
VQM files, you can make multiple VQM files for use with the Quartus II
software and the LogicLock block-based design feature from a single
Synplify Pro software project.
Revision
History
The information contained in AN 165: Synplify and Quartus II LogicLock
Design Flow version 2.0 supersedes information published in previous
versions.
Version 2.0
The following changes were made in AN 165: Synplify and Quartus II
LogicLock Design Flow version 2.0:
■
■
■
■
Added information on the Multipoint feature introduced in Synplify
7.2.
Added information on the LogicLock design flow to make the
document consistent with other application notes.
Added three new figures to document.
Added and repaired tables from new information additons.
Version 1.2
The following changes were made in AN 165: Synplify and Quartus II
LogicLock Design Flow version 1.2:
■
■
Made minor corrections to page 1.
Updated list of devices in procedure on page 5.
Version 1.1
The following changes were made in AN 165: Synplify and Quartus II
LogicLock Design Flow version 1.1:
■
18
Updated Synplify version number
Altera Corporation
AN 156: Using General-Purpose PLLs with APEX II Devices
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19
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