®
November 2002, ver. 1.2
Using CDS in
APEX II Devices
Application Note 157
Introduction
Expansion in the telecommunications market and growth in Internet use
is creating a demand to move more data faster than ever. To meet this
demand, system designers rely on solutions such as differential signaling,
and emerging high-speed interface standards such as RapidIO,
POS-PHY 4, and Utopia IV.
Preliminary
Information
The high-speed interface I/O pins in APEX II devices integrate differential
I/O into the programmable logic device (PLD) to quickly move data. They
also utilize a state-of-the-art CMOS process that consumes far less power
than GaAs devices, the other high-speed alternative.
AN 166: Using High-Speed I/O Standards in APEX II Devices provides
information on APEX II device high-speed I/O standard features and
functions. This document also explains how system designers can take
advantage of these standards to increase system efficiencies and
bandwidth.
Clock-Data
Synchronization
APEX II devices offer four high-speed differential I/O banks, two
transmitter banks, and two receiver banks. Each bank contains
18 channels and one clock. Each channel is designed to transfer data at
rates up to 1 gigabyte per second (Gbps) and support several topologies.
When distributing clocks at high speeds and supporting multiple
topologies, a solid solution is needed for clock-to-data skew.
Trace lengths, trace capacitive loading, variations in threshold voltages,
and transmission-line terminations may cause clock and data signals to
arrive too early or too late, causing skew. This problem can cause
inaccurate data transmission from one point to another and interrupt
communication between components within the system.
A system running at lower speeds may not require synchronization since
skew is not a major factor in the overall cycle time. However,
synchronization becomes important with high-speed systems as timing
budgets become tighter.
Altera Corporation
AN-157-1.2
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AN 157: Using CDS in APEX II Devices
Preliminary Information
In general, a clock-data synchronization (CDS) solution is highly desirable
because it provides superior flexibility to system designers. CDS
synchronizes the incoming data stream to the system clock regardless of
what the skew may be between the clock signal and data stream. CDS can
compensate for as much as 50% of skew in single-bit mode and can
compensate for unlimited skew in multi-bit mode.
APEX II High-Speed Interface Bus Topologies
The term topology refers to the physical or logical arrangement of a
network or a telecommunications system. The APEX II high-speed
interface enables multiple system topologies.
The APEX II high-speed interface structure can receive clocks from up to
two sources. Several APEX II devices can share a single clock source to
create a variety of system configurations. This section describes popular
system topologies that the APEX II device’s high-speed interface
supports.
Point-to-Point Topology
In a point-to-point topology, two devices are connected to each other (see
Figure 1). In this configuration, the clock is forwarded to the destination
where it deserializes the transmitted serial data stream. This is usually the
simplest form of transmission, since the electrical components, from one
point to another, are easily measured and the resulting skew is easily
analyzed. Point-to-point topology can use single-bit CDS to compensate
for skews as great as 50% of the data-bit period.
Figure 1. Point-to-Point Topology
Data
Signals
APEX II
Device
APEX II
Device
Clock
Signal
Single-Clock Synchronous Topology
The single-clock synchronous topology uses a single master clock to
synchronize all devices. This clock can be shared by two or more devices
or used throughout the entire system.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Since elements such as unequal PCB trace routing, device-to-device delay
variation, clock duty cycle, or package-trace skew create or increase skew
when this topology is utilized, the data will not arrive at the same time as
the clock. Multi-bit CDS uses internal circuits to adjust for the phase
difference between the incoming clock signal and the data stream.
However, the receiver and transmitter must have the same frequency.
Figure 2 shows a hypothetical scenario where clock frequency is at
100 MHz and the deserialization factor is set to 10. Data may not be
captured correctly because the skew between clock source and data lines
is more than the allowed receiver skew margin (RSKM). The APEX II
device’s CDS system solves these system problems.
Figure 2. Single-Clock Synchronous Topology
APEX II
Device 1
Data
Data
APEX II
Device 2
Data
APEX II
Device 3
APEX II
Device 4
Clock
Signal
Switch Topology
The switch topology utilizes a central point of control (see Figure 3). Each
station or device in the telecommunications system communicates via
point-to-point wiring to this central link. The central control switch
receives data from each node and then routes it to the node addressed to
the data.
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AN 157: Using CDS in APEX II Devices
Preliminary Information
When designing a system based on a switch topology, designers typically
must keep track of clock duty-cycle, variations in threshold, edge-rate
mismatch between clock-and-data output cells, and the overall skew
between data and clock. All of these variables make it difficult for a
designer to create a board layout. However, the APEX II device’s multi-bit
CDS solves these issues by eliminating skew between the clock and data
for each device and each channel.
Figure 3. Switch Topology
Data
Data
APEX II
Device
APEX II
Device
Data
Data
Data
APEX II
Device
Data
APEX II
Device
Data
APEX II
Device
Data
Clock
Signal
Matrix or Mesh Topology
A matrix or mesh topology is a communications network where at least
two pathways run between each node (see Figure 4). This topology is
typically used for a small network. However, the APEX II device’s CDS
feature allows designers to implement a matrix or mesh topology in a
larger network.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Figure 4. Matrix Topology
Data
APEX II
Device
Data
Data
Data
Data
Data
APEX II
Device
APEX II
Device
Data
Data
Data
Data
Data
Data
APEX II
Device
Clock
Signal
CDS
Functionality
To use the CDS feature, turn the CDS circuit on, then transmit a known
data pattern (the training pattern). The CDS feature uses the training
pattern to synchronize the data to the clock. CDS can compensate for skew
up to 50% of the bit period with single-bit synchronization or unlimited
skew with multi-bit synchronization by choosing an appropriate phase of
the internal bit clock. See Figure 5.
The APEX II high-speed interface uses an internal over sampling circuit to
precisely capture the data stream. The data for each channel is captured
by five or eight internally generated clock signals (depending on the CDS
mode). This captured data is then compared against a pre-selected
pattern.
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AN 157: Using CDS in APEX II Devices
Preliminary Information
Figure 5. CDS Flow
Clock Signals
APEX II
Input Buffers
APEX II
Input Registers
CDS Data Pattern
Data Pattern
Examination
Select Clock Phase
CDS
Synchronization
Three synchronization techniques are offered in APEX II devices: singlebit, multi-bit, and pre-programmed CDS. The synchronization techniques
are user selectable for each channel.
Single-Bit CDS Synchronization
In single-bit synchronization, a known data pattern is transmitted to the
receiver device(s) for a minimum of three clock cycles. Within the
receiver’s CDS circuitry, the incoming clock input is replicated five times,
each with 90° of phase shift relative to the previously replicated clock. All
five clocks capture the training pattern. The clock that captured the
training pattern most accurately is selected for capturing the actual data.
Figure 6 shows the relationship between the incoming receiver clock,
data, and the five internally generated clocks.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Figure 6. Single-Bit CDS Clocks & Data Input
Clock Input
Data Input
Clock A
Clock B
Clock C
Clock D
Clock A’
Multi-Bit CDS Synchronization
Multi-bit synchronization requires an alternating ones and zeros pattern.
Similar to the single-bit circuitry, various internal phase clocks are
generated. Since the intention is to correct for more than a full bit of skew,
the input clock is replicated eight times to extend the sampling window
into the next bit. Unlike the single-bit synchronization, byte alignment is
not preserved using multi-bit synchronization. Internal function must be
created from logic elements (LEs) for byte alignment.
Figure 7 shows the relationship between the incoming receiver clock,
data, and the eight internally generated clocks.
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AN 157: Using CDS in APEX II Devices
Preliminary Information
Figure 7. Multi-Bit CDS Clocks & Data Input
Clock Input
Data Input
Clock A
Clock B
Clock C
Clock D
Clock A’
Clock B’
Clock C’
Clock D’
Synchronization
Implementation
Before implementing clock-to-data synchronization, designers should
evaluate system requirements and select the CDS method which fits the
design. For example, the pre-programmed CDS method is the simplest
and fastest because no training pattern is required. However, this method
may not be useful for systems where measure skew is difficult.
Pre-Programmed CDS
Designers can use time domain reflection (TDR) techniques, a simple
signal integrity software, or a PCB layout tool to calculate clock-to-data
skew. The skew number can be used to determine which clock best
captures the incoming data stream. CDS may be pre-programmed for
each channel, eliminating the need to send training patterns.
Pre-programmed CDS is useful for systems that cannot send a training
pattern. For example, when a network tester is plugged into a network, it
immediately receives data and cannot transmit a training pattern.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
The pre-programmed CDS method can compensate for clock-to-data
skew up to 50% of a bit period without using extra alignment circuitry.
The resolution of pre-programmed CDS is 25% of the data bit. Because
pre-programmed CDS is used when the amount of board skew is known,
designers can choose the appropriate clock phases to successfully capture
the streaming data at the receiver. Five clock phases (–180º, –90º, 0º, 90º, or
180º) may be selected for each channel. Figure 8 shows three possible
scenarios. The third waveform in Figure 8 shows when skew is larger than
+ 50% of the data bit period. Design connection from the receiver to
internal logic must account for data misalignment.
—180o
—90o
o
0
o
90
o
180
Figure 8. Clock Phase Settings
X1 CLOCK
Skew: 0%
CDS Setting: 0…
0
1
Skew: 50%
CDS Setting: 180…
Skew: 125%
CDS Setting: 90…
9
0
1
2
1
7
8
9
0
7
8
9
8
4
5
6
2
4
5
6
7
3
5
6
3
4
2
3
2
Single-Bit Synchronization Implementation
This mode is best utilized when the skew between clock and data is
estimated or measured to be less than 50% of a bit period. The single-bit
synchronization is then employed to correct a fixed skew by up to 50% of
the data period.
A calibration pattern is required to phase-align the clock with the
incoming data. The calibration data length depends on the operating
mode of the PLL or the W value. W must equal J to use the single-bit
synchronization mode. The calibration pattern is shown in Table 1.
Table 1. Calibration Data Pattern for CDS Single-Bit Circuitry (Part 1 of 2)
PLL ClockBoost
Multiplication/Deserialization Factor
Altera Corporation
Calibration Pattern
10
0000011111
9
000001111
8
00001111
7
0000111
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AN 157: Using CDS in APEX II Devices
Preliminary Information
Table 1. Calibration Data Pattern for CDS Single-Bit Circuitry (Part 2 of 2)
PLL ClockBoost
Multiplication/Deserialization Factor
Calibration Pattern
6
000111
5
00011
4
0011
A dual-purpose CDS pin places all 36 high-speed channel inputs into
calibration mode. The calibration pattern must be driven in for at least
three clock cycles while the CDS pin is set high. The CDS pin is sampled
on the rising edge of the input clock.
Each channel is calibrated separately to compensate for differences in
routing as a result of the PCB layout. To reduce down time, all channels
are calibrated simultaneously. When all channels have been successfully
calibrated, the data channels are ready to receive data. In this mode, the
inputs are byte-aligned, so additional byte alignment is not required. The
timing relationship between the RX_CDS_ENA pin, clock input, and data
is illustrated in Figure 9.
Figure 9. Single-Bit CDS in ×10 Multiplication
Minimum Cycles
RX_CDS_ENA
Clock Input
Receiver Data Input
x x 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0
Calibration Pattern Generation
An APEX II device transmitter or third-party device can send calibration
patterns to receiver data inputs, however, transmitter output bit
orientation may not be aligned with the clock rising edge. Designers
should anticipate misalignment and generate the correct pattern at the
transmitter’s parallel input. For example, the APEX II serializer transmits
parallel data with the first two bits of the previous cycle. The input for the
transmitter should be 00111100 when the serialization factor is eight.
Figure 10 shows the bit orientation relative to the rising edge of the clock.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Figure 10. Bit Orientation of the Transmitter’s Output
0
0
1
1
1
1
0
0
Serilization
Circuit
11110000
Multi-Bit Synchronization Mode
Multi-bit synchronization mode is utilized when skew between clock and
data is unknown or estimated to be more than one full bit period or when
two or more devices drive into one APEX II differential receiver block.
Multi-bit synchronization allows designers to correct any fixed clock-todata skew.
In single-bit CDS, the receiver device distinguishes and correctly aligns
the incoming byte boundaries. In multi-bit CDS mode, only the skew
between the clock and data is corrected, and a separate procedure must be
implemented to realize the byte boundaries.
The procedures for correcting skew between clock and data in multi-bit
CDS is similar to the single-bit CDS procedure, except that the training
pattern alternates ones and zeros for three clock cycles or more,
depending on the estimated skew between clock and data channels. For
example, if the skew is estimated to be in the range of five to six ns and the
data period is only one ns, the training pattern should be repeated for at
least six times to ensure that all channels have received the training
pattern and that the correct clock phase has been selected.
Table 2 shows that the training pattern may start with a zero or a one and
W and J do not have to be equal.
Table 2. Calibration Training Pattern for Multi-Bit Circuitry
PLL ClockBoost
Multiplication/Deserialization Factor
Calibration Pattern
1, 2, 4 to 10
0101010101
1, 2, 4 to 10
1010101010
Figure 11 displays the timing relationship between an RX_CDS_ENA pin,
clock input, and a data pin when a ×10 multiplication rate is utilized.
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AN 157: Using CDS in APEX II Devices
Preliminary Information
Figure 11. Multi-Bit CDS Timing Including RX_CDS_ENA Signal
Minimum Cycles
RX_CDS_ENA
Clock Input
x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Receiver Data Input
Multi-Bit Byte Alignment Circuit
The multi-bit byte alignment circuit determines the byte boundaries of the
parallel data (see Figure 12). The circuit uses the hexidecimal number A1
(10100001 in binary) as the alignment pattern. The device implements
the multi-bit byte alignment circuit in LEs.
f
For a sample design written in VHDL, visit the Altera web site at
http://www.altera.com.
The byte alignment circuit is divided into five main sections with five
tasks:
■
■
■
■
■
Register the parallel data for comparison against the A1 alignment
pattern
Compare the parallel data against the A1 alignment pattern
Control the flow of data by acting as a state machine
Act as a barrel shifter to align data
Transfer data for the logic array interface
Figure 12. Byte Alignment Circuit Block Diagram
Serial
In
Parallel
Out
LE
Register
A
Initiate
Internal Logic
12
Compare
Data vs.
10100011
State
Machine
Detect
10100011
Barrel
Shifter &
Data
Transfer
APEX II
Core
Enable
Pattern Found
Internal Logic
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Register
The parallel data outputs of the serializer and deserializer are connected
to the inputs of an eight input register. The output signals from the
serializer, deserializer, and register A are connected to the comparator
block. Figure 13 illustrates the connection between the two blocks.
Figure 13. Data Flow Between Two Blocks
Serial
Data
Q[7..0]
Serializer/
Deserializer
A[7..0]
Register A
Clock
Compare
Incoming Data
vs. HEX A1
D[7..0]
B[7..0]
Register B
Compare
The comparator’s circuit consists of eight identical AND gates. The AND
gates are configured so that their output is set high only when a
hexadecimal A1 (binary 10100001) value is detected on their input pins.
Every shifted possibility of the hexadecimal value A1 is detected by at
least one of the eight AND gates. Table 3 shows the possible shifted
versions of hexadecimal A1, which are transmitted by the serializer and
deserializer circuit and examined by the compare circuit.
Table 3. Possible Hex A1 Combinations (1)
Altera Corporation
Q[7..0]
A[7..0]
Result
10100001
10100001
Aligned
x1010000
1xxxxxxx
1 bit late
xx101000
01xxxxxx
2 bits late
xxx10100
001xxxxx
3 bits late
xxxx1010
0001xxxx
4 bits late
xxxxx101
00001xxx
5 bits late
xxxxxx10
100001xx
6 bits late
xxxxxxx1
0100001x
7 bits late
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AN 157: Using CDS in APEX II Devices
Preliminary Information
Note to Table 3:
(1)
An x denotes a “don’t-care” bit.
The output of one of these eight AND gates is stored in register B and used
to trigger the state machine which starts the selection process. Figure 14
shows the parallel data flow into register A and into the eight
comparators.
State Machine
The state machine consists of a user-control input pin, a counter, and a
mux, which control the flow of data from the output of the deserializer to
the core logic. The control input pin notifies the state machine that the byte
alignment sequence has begun. It then stays in its initiate mode until the
calibration pattern has been found, at which point, it generates an output
signal indicating that the pattern has been found.
Figure 14. State Machine
Initiate
Start byte alignment
Search
Search for A1 to appear
and exit when it is
found
Send
Send signal to
multiplexer circuit to
allow data flow into
logic array
Barrel Shifter & Data Transfer
The multiplexer circuit is the interface circuit between Register B and the
APEX II logic array. The state machine output is connected to the enable
pins of eight identical flip-flops shown in Figure 15. These flip-flops send
signals to the select input pins of eight identical multiplexers. When the
eight flip-flops are enabled by the state machine, the correct multiplexer is
turned on. The data present on that particular multiplexer is then sent into
the logic array.
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Preliminary Information
AN 157: Using CDS in APEX II Devices
Figure 15. Flip-Flops Controlled By State Machine
B0
B1
D
Q
D
B7
Q
D
DB[7..0]
Connect to Mux
Select Lines S[7..0]
Q
Figure 16 shows the connection to one of the eight multiplexers. In
Figure 16, the multiplexers receive information from the state machine
and rearrange the incoming data. The reconstructed data is then sent to
core logic.
Figure 16. Data Multiplexer
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
S0 S1
Q0
Q1
S2
S3
S4
S5
S6 S7
Q2
Core 0
Q3
Q4
Q5
Q6
Q7
Using CDS &
Byte Alignment
Circuit
Altera Corporation
Since the byte alignment circuit is required only when byte boundaries are
not defined, byte alignment is used only when multi-bit alignment is
used. For single-bit alignment, follow the below steps:
1.
Build a receiver block using the Quartus II MegaWizardTM Plug-In
manager.
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AN 157: Using CDS in APEX II Devices
Preliminary Information
2.
Choose USE Single Bit Mode or Multi-Bit Mode (Clock Data
Synchronization (CDS) option).
3.
Assert CDS pin to a high (1) state for a minimum of three clock
cycles.
4.
Send the required CDS pattern to the receiver.
5.
De-assert the CDS pin.
If the device is programmed for multi-bit mode, the byte-alignment circuit
must be used to find byte boundaries. Follow the below steps:
1.
Set the module’s reset input pin high. This pin clears the byte
alignment circuit.
2.
Set the alignment pin high for one clock cycle.
This command signal tells the byte alignment logic to look for hexidecimal
pattern A1 when performing a byte alignment. An output signal from the
byte alignment circuit goes high when the A1 pattern has been found and
the barrel shifter has been set to align for data.
When the A1 pattern has been detected, the byte_align_done signal
changes state. You can begin sending data. The byte alignment circuit
reconstructs the data and then transfers it to the core logic. Figure 17
shows the output of the ModelSim® software vector simulation. For
simulation purposes, the A1 pattern and the proceeding data were
misaligned by seven bits. The byte_align signal was asserted high for
one clock cycle. The circuit detected, corrected, and reported the A1
pattern misalignment by setting the output byte_align_done signal to
high. Alignment may be repeated at any time during the operation by
asserting the align pin high.
Figure 17. ModelSim Vector Simulation
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AN 157: Using CDS in APEX II Devices
Preliminary Information
The byte alignment circuit and Quartus II software implementation
information is available at http://www.altera.com. The reference design is
implemented for an 8-bit wide circuit but can easily be modified for other
widths.
Summary
The APEX II device CDS system reduces the time designers spend on
timing issues caused by clock-to-data skew. The APEX II device’s highspeed I/O interface allows versatility and a true solution to clock-to-data
skew through the CDS feature.
Revision
History
The information contained in AN 157: Using CDS in APEX II Devices
version 1.2 supersedes information published in previous versions.
Version 1.2
The following changes were made to AN 157: Using CDS in APEX II
Devices version 1.2: changed CDS signal name to RX_CDS_ENA.
Version 1.1
The following changes were made to AN 157: Using CDS in APEX II
Devices version 1.1:
■
■
Figure 9 has been updated
Figure 11 has been updated
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