Foreword
In 1970, when I began my career in
semiconductors, gate oxide thickness was 120 nm, Vdd
was -12 V, and gate lengths were 10 Jim (called
0.4 mil in 1970). Howard Huff and Nick Holonyak
capture the heady excitement of the early days of
integrated circuit fabrication in the opening papers of
these proceedings. In 1970, measurements were a
major challenge: measurement of oxide thickness and
measurement
of
gate
length.
Materials
characterization was also a major challenge: Sodium
in the gate oxide was a particularly nettlesome
problem. Then, as now, measurement of ever
shrinking feature size and characterization of new
materials were key enablers to the advancement of
technology. In the intervening 30 years, feature sizes
have shrunk by 200x (Gate length from 10 jam to
50 nm), and the commensurate measurement and
characterization challenges have become ever more
demanding. In the 70's, airborne contamination layers
were hundreds of angstroms thick. Now, the layers are
only a monolayer and are not detected by current
optical methods, limiting yields at the most recent
technology nodes. Ultra-sensitive surface analysis in
concert with high resolution chemical speciation are
required to identify and quantify this type of elusive
and insidious source of defects. As this example
shows, technological advances in characterization and
metrology are continually required, in order to insure
high impact through the enabling role they play in
progress of the industry.
silicon and high-K materials where the interface is a
significant fraction of the total film thickness and (ii)
high-K diffusion characteristics within two nanometers
of the dielectric interface.
Defects: The defect problems of the 70's have
largely been solved. But as layers become thinner, and
new materials are introduced, new defect issues
emerge:
•
Gate insulators discussed above
•
Barrier layers for Cu metallization
•
Cu itself
•
LOW-K dielectrics
•
Stress-induced defects in Si
•
Monolayer molecular contamination
CD Control: There is a major section of the
proceedings devoted to lithography and gate
patterning. Today, not only is gate CD of critical
importance, but also the profile of the gate in three
dimensions is important. Measurement of this 3-D
profile requires complex AFM and DUV scatterometry
techniques to be developed and implemented in
manufacturing.
Shallow Junctions: The dopant behavior in ultra
shallow junctions depends on interaction with the
surface, and surface preparation and characterization
become increasingly important. At the same time,
measurement of dopant atoms becomes more difficult.
The transition layer at the surface is becoming a
significant fraction of the total dose in ultra shallow
junctions.
The current conference proceedings provide an
excellent summary of the measurement and
characterization challenges today:
Gate Dielectric: The very large number of papers
in these proceedings reflects the challenge posed by
gate dielectric characterization. Not only are today's
gate dielectrics 4-5 atomic layers thick, and becoming
thinner, but characterization of nitrogen dose and
depth profile through these ultra-thin silicon oxide
layers is required in production.
Moreover,
introduction of new high-K materials poses demanding
characterization
challenges
associated
with
understanding (i) interfacial interaction between
Stress: Stress is becoming increasingly important
because, at small dimensions, stress in the conduction
channel is increasing and is affecting to a larger degree
channel mobility and drive current. Techniques to
nondestructively measure stress at the 1-10 nm scale
need to be developed.
Xlll
In-line Measurement and Characterization: The
new measurement and characterization techniques that
are being developed to deal with ever shrinking
dimensions and new materials are finding their way
into wafer fabs as in-line measurement tools as
indicated by several of the conference papers.
Grand Challenges: Silicon technology as we
know it is approaching the end of Moore's Law
scaling. Pessimists predict the demise of Moore's Law
scaling within the next 10-15 years. Optimists argue
that there is no cause for alarm, and that scaling will
continue for at least 10-15 more years. Both optimists
and pessimists agree that we are approaching atomic
dimensions. Both agree that it is impossible to make a
gate insulator thinner than a couple of atomic layers.
Both understand that dopant atoms are spaced a
minimum of 4 nm apart, and that it is not feasible to
control the threshold of a 4 nm device with dopant
atoms. Silicon CMOS is indeed approaching the
atomic limit of the constituent materials, and as we
approach those limits the Grand Challenges for
measurement and characterization are to measure
individual atoms and to characterize materials in terms
of the positions of the atomic nuclei and the
distribution of electrons at atomic dimensions.
Finally, let me say that this book needs to be on the
shelves of those of us who believe that metrology
advances are critical to the continued advances in
semiconductor technology. The authors and editors
should be commended for making an outstanding
contribution to the semiconductor industry by
assembling such a magnificent compendium of
excellent papers.
Dennis Buss, Vice President, Silicon Technology
Development, Texas Instruments
June 2003
xiv