In-line, Non-destructive Electrical Metrology of Nitrided
Silicon Dioxide and High-k Gate Dielectric Layers
Robert J. Hillard^ P.Y. Hung*, William Chism*, C. Win Yef, William H.
Rowland^ Louison C. Tan^ and Christine E. Kalnas1^
1
*Solid State Measurements, Inc.
110 Technology Dr.
Pittsburgh, PA 15275
^International Sematech Corp.(ISMT)
Montopolis Dr.
Austin, TX
Abstract. Highly sensitive, accurate and precise methods for measuring the properties of dielectrics used in sub
0.13 jam technology are required. It is particularly critical to monitor the electrical properties of the gate dielectric. The
electrical properties of thin dielectrics are assessed with a new, non-contaminating, non-damaging elastic probe. This
probe forms a small diameter (-30 um to 50 um ) Elastic Metal gate (EM-gate) on the surface of a dielectric.
Subsequent electrical measurements are made with advanced Capacitance-Voltage (CV), Conductance-Voltage (GV),
and Current-Voltage (IV) techniques. Valuable and essential information about the dielectric thickness and quality,
leakage current, Si-SiO2 interface quality, and channel carrier density profile is obtained.
drive currents, respectively. It is also highly desirable
to monitor other device related parameters such as
interface trap density (DIT), threshold voltage (VT),
flatband voltage (VFB), channel threshold adjust Partial
Implant Dose (PID) and surface dopant density
(NSURF), and for alternate high-k dielectrics, CV
hysteresis (AVFB).
INTRODUCTION
Current device technologies require the use of thin
oxides and oxynitrides for active gate dielectrics that
are between 20 Angstroms and 30 Angstroms in
thickness. Future technology nodes (0.10 jim and
below) will require an Equivalent Oxide Thickness
(EOT) that is between 15 Angstroms and 20
Angstroms. Looking even further ahead to 0.05 |im
technology, gate dielectrics will be required to have an
EOT of 10 Angstroms and less (1). At this point,
alternate, high dielectric constant (high-k) gate
dielectrics will be used. These high-k dielectrics offer
the advantage of a high capacitance density (small
EOT) and low gate leakage currents due to the higher
physical thickness of these films.
Conventional capacitance-voltage (CV) techniques
require a polysilicon or metal gate Metal Oxide
Semiconductor Capacitor (MOSCAP). These require
additional processing which is time-consuming.
Furthermore, these conventional methods are highly
affected by equivalent circuit effects introduced by
large direct tunneling leakage currents, series
resistance, and stray inductance influences, and by
material effects such as polysilicon depletion. It is
highly desirable to develop an accurate and repeatable
method that is rapid, non-contaminating, and
non-damaging, allowing it to be used on product
wafers. This method must be free from the equivalent
circuit errors that plague conventional CV
The most important parameters determining device
performance for deep sub-micron (0.13 jum and lower)
processes are the Equivalent Oxide Thickness (EOT)
and Leakage Current (ILK)- These two parameters
dominate the on-state and off-state MOS transistor
CP683, Characterization and Metrology for VLSI Technology: 2003 International Conference,
edited by D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, R. P. Khosla, and E. M. Secula
© 2003 American Institute of Physics 0-7354-0152-7/03/$20.00
796
measurements on thin dielectrics. It is also important
that the measurement technique has a high throughput.
In the case of thin dielectrics, surface contaminants
such as water and organics become adsorbed on the
surface of the dielectric over time and can influence
the measurements. Rapid measurement times reduce
these absorption effects.
compatible metal that deforms elastically to form a
small diameter contact to the surface of a dielectric or
semiconductor. The probe assembly is operated with a
controlled force and descent rate. The kinematic
mounting is highly important to the non-damaging
nature of the system and greatly enhances the
repeatability and lifetime of the probe. The probe
properties, such as material, geometry, and
preparation, are crucial to the probe's performance. It
is critical that the probe is elastic, and therefore
reversible, and is optimized in order to form a planar,
intimate contact to the dielectric. The EM-gates
described in this paper were prepared with a
proprietary process in order to produce a stable,
intimate, and non-damaging and non-contaminating
contact. The nominal areas and diameters of the EMgates are about 10~5 cm2 and 30 to 40 jum, respectively.
This paper discusses a new Elastic Metal gate (EMgate) that allows for quick MOSCAP formation on a
variety of dielectric and semiconductor surfaces.
Subsequent CV, GV and IV measurements can be
made with this new elastic probe and information
obtained relative to the process and device parameters
discussed earlier. EM-gate measurements can be
made on unpatterned wafers and in scribe line test
areas on product wafers. Applications on nitrided
oxides are emphasized, with some examples on high-k
dielectrics.
There are two types of elastic probes commercially
available; type A is optimized for CV measurements,
and types B or C optimized for IV measurements. The
CV probe is designed to have a metallic oxide to allow
for capacitance measurements down to 7 Angstroms.
The IV probe is designed to allow large direct
tunneling currents to flow and is highly suitable for
electrical characterization of thin gate dielectrics.
Each of these probes is described in the next section.
DESCRIPTION OF ELASTIC METAL
GATE (EM-GATE)
EM-gate Basic Description
Drawings of several types of probes that are used to
form the gate of a two-terminal MOSCAP are shown
in Figure 1. These probes can be used to make CV,
GV, and IV measurements.
CV and IV Model
A schematic of two types of elastic probes is shown
in Figure 2.
m
.jliil^r
FIGURE 1. Illustrations of MOSCAPs formed with a) a
polysilicon gate, b) a mercury (Hg) Gate, and c) an EM-gate.
The polysilicon gate MOSCAP construction,
formed with short loop processes, is similar to the final
device structure except that it takes considerable time
to form the gate for monitor wafers. In the case of test
devices at first metal, this process step is far from gate
oxidation and therefore does not provide immediate
feedback to the process and development engineer.
The mercury (Hg) gate MOSCAP shown in Figure Ib
is highly useful for development and R&D MOS
applications (2), but is not appropriate for use on inline monitoring of product wafers because of the
possible mercury contamination in fab. The elastic
metal gate shown in Figure Ic is non-contaminating
and non-damaging, and can be used on either product
or monitor wafers. It is made with a semiconductor
a.
b.
FIGURE 2. Schematic of two types of elastic probes
used for electrical characterization. The type B or C probe
used for IV measurements is shown in Figure 2a. The type A
elastic probe used for CV and GV measurements is shown in
Figure 2b.
797
The type A probe shown in Figure 2b is used for
making CV measurements on thin dielectrics and is
highly robust against direct tunneling (DT) leakage
current due to the presence of the metallic oxide layer
on the probe. This metallic oxide layer effectively
increases the injection barrier height, thereby lowering
carrier transmission and current transport.
determine the frequency dispersion associated with
multiple frequency CV measurements. This is the best
test and can detect dissipation factor, near-resonant
frequency errors at higher frequencies, and leakage
current effects at lower frequencies. An example of an
EM-gate multiple frequency CV measurement made
on a thin high-k dielectric is shown in Figure 4.
The effectiveness of this metallic oxide layer in
reducing DT leakage current is shown for the
simulated IV curves in Figure 3. An assumed
dielectric constant of k = 1 was used. As seen in
Figure 3, the current is significantly reduced as the
interface layer thickness increases.
20
EM-gate Multi-frequency Comparison
____Thin High K HfO2_______
Frequency Range: 5 KHz to 1 MHz
Note: HP-4284A Used
15
EM-gate IV Simulations
Interface Barrier Dependence
O 10
3.5
2.5
1.5
0.5
Gate Voltage (V)
FIGURE 4. EM-gate multiple frequency CV measurements
made on a thin HfO2 high-k dielectric. The absence of CV
roll-off or vertical shifts in accumulation verifies that the
measurement is free from equivalent circuit effects within the
range of frequencies, 5 KHz to 1.0 MHz.
Vg (V)
The second test is the series-corrected capacitance
versus parallel capacitance at a given measurement
frequency (6). If the CV data are affected by
equivalent circuit effects, the series-corrected
capacitance and parallel capacitance data in
accumulation will not agree.
FIGURE 3. Simulated IV plots as a function of interface
layer thickness. The existence of a controlled interface layer
inhibits DT leakage current and allows for CV measurements
on sub-10 Angstrom oxides and SiON.
Type A EM-gate probes have been used to measure
CV data on SiO2 and SiON dielectrics as thin as 7
Angstroms (3).
EM-gate IV measurements are sensitive in cases
where DT currents dominate, that is, for oxides with
thicknesses less than about 35 Angstroms. The type B
and C probes are essentially DT sensing probes.
Probe Calibration
The probe is calibrated for an effective contact area
and for the presence of a metallic oxide on the probe
tip. The parallel capacitance associated with the probe
and cabling is determined and accounted for.
Other equivalent circuit effects, such as series
resistance and stray inductance, that cause errors in
conventional CV measurements have only minor
effects in EM-gate CV measurements. This is
primarily because the EM-gate effective area is small
(~10~5 cm2). EM-gate CV data is affected only by
series resistances greater than 2 kQ. Similarly, large
stray inductances (>50 |LiH) are required to induce
near-resonant frequency effects. SPICE simulations
have also confirmed these effects (5).
EM-gate CV and GV Curves
Schematics of EM-gate conventional CV and GV
curves are shown in Figures 5 and 6, respectively.
Several tests can be made to check for the influence
of equivalent circuit effects. The first test is to
798
rapid, repeatable, and highly sensitive to processing
conditions and interface quality.
Capacitance
One concern with measuring thin dielectrics is the
effect of the measurement itself on the parameters
being measured. It is well known that interface trap
and oxide trapped charge densities can change with
electrical stress (7). EM-gate CV measurements can
be made under low stress conditions, thereby
significantly reducing both the electrical stress and the
time for the measurements.
[Reverse CV]
[Forward CV]
Gate Voltage
FIGURE 5. Conventional forward and reverse CV curves.
Repeatability
EM-gate CV measurements are made by starting
in accumulation and sweeping the voltage to deep
depletion as shown in Figure 5. After establishing
equilibrium, a reverse CV curve is acquired. These
curves provide valuable information on Capacitive
Effective Thickness (CET), EOT, VFB, VT,cv, AVFB,
Typical short term area repeatability obtained
from ten measurements made at the same site, raising
and lowering the probe before each measurement, is
between 0.1% and 0.3% (one sigma). The typical
short term repeatabilities obtained for carrier density
and VT adjust PID (Partial Implant Dose) are less than
1.0% (one sigma); three-day repeatabilities for CET
and VFB are 0.1 Angstroms and lOmV, respectively.
An example of an EM-gate short term CET
repeatability test is shown in Figure 7. This test was
performed by making 15 measurements in a local
region with a separation of 0.1 mm between specific
measurement locations.
and NSURF-
Conductance
Sensitive to Leakage
And Series Resistance
Sensitive to Interface
Trap
Density (D|T)_____
Series Resistance
Corrected G
40
EM-gate Short Term Repeatability Test
8 Angstrom SiON Wafer____
Mean = 9.83 Ang.
Sigma = 0.051 Ang.
30
Gate Voltage
^5 20
FIGURE 6. Conventional parallel- and series-corrected GV
curves.
o
10
A description of an EM-gate forward GV
measurement is shown in Figure 6. GV data in
accumulation are highly sensitive to series resistance
and leakage current (6) which represent the real, inphase currents and voltages from the wafer under test.
An additional conductance component comes from the
interaction of interface traps with the applied ac signal
(7).
From the peak series-resistance-corrected
conductance, a DIT value can be obtained at a specific
energy. The energy value depends on the applied
frequency and sample dopant density and is defined by
the DC gate bias at which the peak conductance
occurs. The single frequency GV-based method for
measuring DIT cannot provide spectroscopic
information about DIT versus energy. However, it is
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
Gate Voltage (V)
FIGURE 7. EM-gate short term CET repeatability test
made on a SiON wafer with an optical thickness (OTox) of
8 Angstroms. The one sigma CET repeatability obtained
from this test was 0.051 Angstroms. These statistics are
based on 15 local measurements made 0.1 mm apart.
799
important to monitor the dielectric or gate leakage. An
example of EM-gate IV measurements made on thin
SiO2 and SiON dielectrics is shown in Figure 10.
EM-gate IV measurements are highly sensitive to
SiON and to direct tunneling currents. A plot of
measured leakage (50% cumulative probability) versus
optical thickness obtained from IV wafer maps is
shown in Figure 11 for both the SiON and SiO2
dielectrics. The observed sensitivities of about 3 to 4
Angstrom/Decade are typical for EM-gate IV leakage
current measurements.
Oxide (SiO2) and Nitrided Oxide
(SiON) Applications
EM-gate CV, GV and IV measurements were
measured on SiO2 and SiON dielectrics with optical
thicknesses in the range of 13 to 20 Angstroms. EMgate CV curves acquired for SiON wafers with and
without an anneal are shown in Figure 8.
EM-gate CV: SiON Dielectrics
10
EM-gate IV Comparison
Annealed
Not
Annealed
c
-2
-1.5
Vg(V)
-0.5
FIGURE 8.
EM-gate CV curves obtained on SiON
dielectrics with and without an anneal.
-10-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
-0.0
Vg(V)
The distortion in the un-annealed CV curves is
due to oxide trapping (8) and the effects of a high D]T.
The EM-gate EOT values were in the 15 to 17
Angstrom range on the annealed wafers.
The
influence of the post-oxidation/nitridation anneal can
be clearly seen in Figure 8. The corresponding GV
curves obtained from the same CV sweep are shown in
Figure 9. The significantly increased peaks in the unannealed conductance curves are due to a high
interface trap density.
FIGURE 10. EM-gate IV curves measured on thin SiO2
gate dielectrics.
EM-gate Leakage Current
50 % Cumulative Probability
1 .OOE-03
—————————————————————————
10
15
2
20
•y 1.00E-04
g- 1.00E-05
EM-gate GV: SiON Dielectrics
0)
o>
| 1.00E-07
*V»
y=0.0388e°-6548x
/ ^"sXr——
y = 0.0269e°-6921x
R2 = 0.9988
R2 = 0.9975
N^v
(3.33Ang./Decade)
Otox (Ang.)
N«
^fc
•
•
—
—
SiO2
SiON
Expon. (SiO2)
Expon. (SiON)
FIGURE 11. EM-gate IV 50% cumulative probability
leakage current versus Optical Thickness (OTox) for SiO2
and SiON dielectrics. Typical leakage current sensitivities
of about 3 to 4 Angstroms/Decade are observed.
High-k Gate Dielectrics Applications
Application of the CV and IV measurements from
EM-gate on the characterization of high-k dielectrics
was also explored. The best results are obtained on
those high-k dielectrics that have surface roughnesses
comparable to good quality SiO2 or SiON films. An
example of EM-gate CV measurements made on
FIGURE 9. EM-gate GV curves obtained on SiON
dielectrics that have been properly annealed and with no
anneal.
Although EM-gate CV and GV measurements are
highly useful for characterizing the electrical thickness
of thin dielectrics and the interface quality, it is also
800
HfSiOx dielectrics with optical thicknesses in the 40 to
50 Angstrom range are shown in Figure 12.
Although applications to high-k dielectrics are
still under development, good sensitivity has been
observed.
REFERENCES
(1) International
Technology
Semiconductors: 2001 Edition.
FIGURE 12. EM-gate CV measurements on thin HfSiOx
high-k dielectrics
(3) SSM Applications Seminar, Yr. 2001.
(4)
An example of EM-gate CV measurements made
on ZrO2 high-k dielectrics is shown in Figure 13.
EM-gate CV Comparison
ZrO2 High k Dielectrics
18
for
(2) B. Roberds and R. J. Hillard, Electrical Characterization
of Advanced Gate Dielectrics with Hg Gate
Capacitance-Voltage (CV) and Current-Voltage (IV),
Electrochemical Society Proceedings Volume 99-16,
pg. 385, The Electrochemical Society, Inc. (1999).
0
-1
Voltage (V)
Roadmap
16
14
R. J. Hillard, R.G. Mazur, S. M. Ramey, W. H.
Rowland, G. A. Gruber, R. Siergiej, and S. Evseev,
Product Wafer Measurements of MOS Gate Dielectric
Quality with a Small Diameter Elastic Probe, AIP
Conference
Proceedings,
Characterization
and
Metrology for ULSI Technology, Vol. 550, 26-29, June
2000.
(5) SSM Seminar 2003, to be published later this year.
12
i10
O
(6) D.K.Schroder, Semiconductor Material and Device
Characterization, J. Wiley &Sons (1990).
8
6
(7) E.H. Nicollian and J.R. Brews, MOS (Metal Oxide
Semiconductor) Physics and Technology, J. Wiley and
Sons (1982).
—— 200 A ZrO2: EOT = 44.7 A
— • • • • 100AZrO2:EOT = 28.7A
— - 50AZrO2:EOT = 21.8A
4
2
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
(8) W.K. Chim and P.S. Lim, IEEE TED, Vol. 47, No. 2
(2000), p. 473.
3.0
Gate Voltage (V)
FIGURE 13. EM-gate CV measurements made on ZrO2
high-k dielectrics.
(9) CVC CV Analysis Software, J. Hauser, NCSU.
High k dielectric EM-gate CV and IV
measurements are still under development; the primary
issues that need to be better understood are the
dependence of CV on surface roughness and the
influence of surface aging.
SUMMARY
FastGate™ CV, GV, and IV measurements have
been demonstrated on a variety of SiO2, SiON, and
high-k dielectric films. EM-gate CV measurements
were shown to be repeatable and highly sensitive to
gate dielectric EOT, nitrogen content, and oxide and
interface quality.
801